View ELANSC310_4785284.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lansc310 microcontroller evaluation board users manual evalbd.book : frt page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board, revision 1.0 ? 1996 by advanced micro devices, inc. all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of advanced micro devices, inc. use, duplication, or disclosure by the government is subject to restrictions as set forth in subdivision (b)(3)(ii) of the rights in technical data and computer software clause at 252.227-7013. advanced micro devices, inc., 5204 e. ben white blvd., austin, tx 78741. amd is a registered trademark, and lan is a trademark of advanced micro devices, inc. other product or brand names are used solely for identification and may be the trademarks or registered trademarks of their respective companies. the text pages of this document have been printed on recycled paper consisting of 50% recycled fiber and 50% virgin fiber; the post-consumer waste content is 10%. these pages are recyclable. advanced micro devices, inc. 5204 e. ben white blvd. austin, tx 78741-7399 evalbd.book : frt page 2 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual iii contents about the lansc310 microcontroller evaluation board features..................................................................................................................x chapter 1 quick start booting dos from a diskette .......................................................................... 1-2 installation requirements.............................................................................. 1-3 board installation .......................................................................................... 1-4 connecting an ide hard drive ......................................................................... 1-7 for more information ....................................................................................... 1-9 chapter 2 board functional description board layout ..................................................................................................... 2-2 evaluation board restrictions........................................................................... 2-4 bios .................................................................................................................. 2-5 systemsoft bios .......................................................................................... 2-6 phoenixpico bios .................................................................................... 2-10 bus modes ....................................................................................................... 2-16 isa mode .................................................................................................... 2-17 local bus mode .......................................................................................... 2-18 evalbd.book : evalbd.toc page iii thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual iv 1.0 memory............................................................................................................ 2-18 dram main memory................................................................................. 2-19 memory voltage setting ............................................................................. 2-19 i/o .................................................................................................................... 2-20 ps/2 mouse.................................................................................................. 2-20 serial ports .................................................................................................. 2-21 parallel port ................................................................................................. 2-21 ide hard drive ........................................................................................... 2-21 roms............................................................................................................... 2-22 power measurement ........................................................................................ 2-23 bl1Cbl4 pins............................................................................................. 2-24 breadboard area.......................................................................................... 2-24 power management ......................................................................................... 2-24 suspend/resume ......................................................................................... 2-25 power management simulation .................................................................. 2-25 micropower off mode .................................................................................... 2-26 chapter 3 using the software systemsoft evaluation diskette.................................................................... 3-1 phoenixpico evaluation diskette ................................................................ 3-1 datalight software evaluation kit diskette.................................................. 3-1 amd utilities diskette ................................................................................. 3-2 elan pmu evaluation utility ............................................................................ 3-4 a: setup pmu mode characteristics (pmcx pins, cpu speed).................. 3-5 b: force pmu state transitions ................................................................... 3-8 c: test battery level & acin pins.............................................................. 3-9 x: restore pmu state and exit to dos........................................................ 3-9 z: leave current pmu values and exit to dos .......................................... 3-9 evalbd.book : evalbd.toc page iv thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual v 1.0 evalset serial and parallel port setup utility ................................................. 3-10 serial port 1................................................................................................. 3-10 serial port 2................................................................................................. 3-10 parallel port 1.............................................................................................. 3-11 usage........................................................................................................... 3-11 memory management system (mms) viewer utility ................................... 3-12 description .................................................................................................. 3-12 scope ........................................................................................................... 3-13 operating instructions................................................................................. 3-13 restrictions on use ..................................................................................... 3-17 register dump utility ..................................................................................... 3-19 chapter 4 developing code programmable general purpose (pgp) pins ..................................................... 4-2 power management control (pmc) pins.......................................................... 4-3 programming bios flash/eprom or application flash/eprom ........................................................................... 4-5 evaluation boards memory map ..................................................................... 4-7 evaluation boards i/o map ........................................................................... 4-10 evaluation boards irq mapping................................................................... 4-11 evaluation boards dma mapping ................................................................ 4-13 evaluation boards components..................................................................... 4-14 enabling the lansc310 internal serial port .................................................. 4-15 evalbd.book : evalbd.toc page v thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual vi 1.0 appendix a evaluation board setup summary setup summary................................................................................................. a-1 appendix b verified peripherals verified peripherals .......................................................................................... b-1 appendix c board layout suggestions board layout suggestions................................................................................ c-1 appendix d schematics schematics ........................................................................................................ d-1 index evalbd.book : evalbd.toc page vi thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual vii 1.0 list of figures lansc310 microcontroller evaluation board ...................................................................... 2-2 list of tables installation troubleshooting ................................................................................................... 1-6 board layout........................................................................................................................... 2-3 systemsoft bios set-up screen options .............................................................................. 2-6 phoenixpico bios main menu setup screen options ....................................................... 2-11 phoenixpico bios advanced menu setup screen options ............................................... 2-13 phoenixpico bios power menu setup screen options ..................................................... 2-14 phoenixpico bios exit menu setup screen options......................................................... 2-15 bus mode selection and affected jumpers .......................................................................... 2-17 i/o address 100C107 .............................................................................................................. 4-2 typical full isa memory map .............................................................................................. 4-8 typical full isa i/o map..................................................................................................... 4-10 typical full isa irq mapping ............................................................................................ 4-12 typical full isa dma mapping.......................................................................................... 4-13 bus mode selection and affected jumpers ........................................................................... a-2 configuration jumpers ........................................................................................................... a-2 jp18........................................................................................................................................ a-3 switches ................................................................................................................................. a-3 power measurement jumpers ................................................................................................ a-4 evalbd.book : evalbd.lof page vii thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual viii 1.0 evalbd.book : evalbd.lot page viii thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual ix about the lansc310 microcontroller evaluation board congratulations on your decision to design with the lansc310 microcontroller! this sophisticated, integrated device is uniquely suited to meet the needs of the next generation of embedded solutions. from its high integration to pc/at compatibility to remarkable power management, the lansc310 microcontroller is the ideal device to enable compact, fully functional, low-power designs with a quick time to market. the lansc310 microcontroller evaluation board has been provided as a test and development platform for lansc310 microcontroller-based designs. most of the possible options and features of the lansc310 microcontroller can be exercised on this board. since there are numerous options available, this board is a much larger form factor than could be achieved with a dedicated set of features. . this evaluation board is provided as a reference only and should only be used to experiment with the design trade-offs of the lansc310 microcontroller, make power measurements, and develop operating and application software. note: advanced micro devices does not assume any responsibility for the maintenance of this evaluation tool. changes to the schematics will only be made if the board is required to go back through a cad layout. refer to the lansc310 microcontroller data sheet and the lansc310 microcontroller programmers reference manual for detailed information on the lansc310 microcontroller. evalbd.book : about page ix thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual x 1.0 features external connectors ? two serial port connections C one internal lansc310 16c450-compatible port (com1 or com2 configurable) C one super i/o 16c550-compatible port (com1 through com4 configurable) ? one parallel port connection from the lansc310 microcontroller ? two 16-bit isa slots (for evaluation of isa-based devices only) ? one ide connector (connected to the lansc310 isa bus) ? one floppy-drive connector (connected to the super i/o floppy-drive controller) ? one at-style keyboard connector (connected to the 8042 keyboard controller) ? one ps/2-style mouse connector (connected to the 8042 keyboard controller) main memory configurations ?dram C 512 kbyte, 1 mbyte, 2 mbyte, 4 mbyte, 8 mbyte and 16 mbyte dram configurations supported C 3-v or 5-v dram support C four standard 30-pin dram simm sockets C one standard, 72-pin dram, 16-bit simm socket (can be used instead of the 30-pin sockets) power management ? power planes are isolated and jumpers are provided to measure current consumption. the cpu voltage sources are: v cc , v ccmem , v ccsys , v ccsys2 , v cc5 , v cc1 , a vcc ? suspend/resume button provided (note that bios enable the suspend/resume function) ? micropower off button provided for testing ? dip switch for transitioning battery-low and acin pins for testing evalbd.book : about page x thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual xi 1.0 bus modes ? full isa mode (full 16-bit isa bus support) ? local bus mode (16-bit bus support for high speed video) bios rom ? two 32-pin dip sockets are provided to allow for bios roms (which socket is enabled is selected via jp32) ? either a 128kx8 or 256kx8 eprom/flash is supported (amds 27c010 or 27c020 eprom, and amds 12-v 28f010, 5-v 29f010, 12-v 28f020, or 12-v 28f020a flash are recommended) ? 12-v programming voltage is available ? evaluation copies of phoenixpico bios and systemsoft bios are provided in the sockets of the evaluation board application rom (dos rom) ? four 32-pin dip sockets are provided for application rom space ? 256kx8 or 512kx8 eprom/rom devices are supported (amds 27c020 or 27c040 are recommended) ? 256kx8 flash devices are supported (amds 12-v 28f020 or 12-v 28f020a flash are recommended) note: 512kx8 flash can be supported after a minor board rework. contact your local amd or distributor field application engineer for more information. ? application rom space is 16-bits wide (two or four devices must be used) ? 12-v programming voltage is available ? datalight rom-dos mini-sdk (software developers kit) is provided with the evaluation kit debugging ? headers for all 208 signals on the lansc310 microcontroller ? supports dos soft ice tools and rom ice tools ? support for standard x86 application debugging tools os support ? compatible with standard 32-bit operating systems ? dos, winlight, windows 3.1, geos, qnx evalbd.book : about page xi thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual xii 1.0 evalbd.book : about page xii thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual 1-1 chapter 1 quick start this chapter provides information that helps you quickly set up and start using the lansc310 microcontroller evaluation board. the lansc310 microcontroller evaluation board is shipped with evaluation bios from phoenix and systemsoft, which have been configured specifically for this board. (a jumper, jp32, selects which bios is used at power-up.) the bios contains the code which allows the lansc310 microcontroller evaluation board to function just like a standard at-compatible pc. the lansc310 microcontroller evaluation board can boot from standard at-compatible diskettes and can use at- compatible displays, display adapters and keyboards. this chapter describes how to set up the lansc310 microcontroller evaluation board in full isa bus mode and boot dos from a diskette. in this mode, the trident isa bus vga card is used to drive a common video monitor. the end of the chapter explains how to connect an ide hard drive to configure your lansc310 microcontroller evaluation board to operate like a standard 386 desktop computer. evalbd.book : ch1 page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-2 1.0 booting dos from a diskette caution: as with all computer equipment, the lansc310 microcontroller evaluation board may be damaged by electrostatic discharge (esd). please take proper esd precautions when handling any board. warning: read before using this evaluation board before applying power, the following precautions should be taken to avoid damage or misuse of the board: ? make sure power supply connectors (from a standard at system power supply) are plugged onto the board correctly. the grounds (usually black wires) should meet at the center of the two power supply connectors on the board. ? see board layout on page 2-3 for important information. ? see appendix b for a list of peripherals that have been used to test the evaluation board prior to shipping. the following documents are updated on an ongoing basis and contain important errata information regarding the evaluation board. ? the evaluation board errata document discusses hardware issues pertaining to the evaluation board.the current version is shipped with the kit; contact your local amd representative for any updates. ? the bios errata document discusses software issues pertaining to the phoenix and systemsoft bios that are shipped with your evaluation board. this document is available through your local amd representative. ! evalbd.book : ch1 page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-3 1.0 installation requirements first you need the following from the lansc310 microcontroller evaluation board kit: ? lansc310 microcontroller evaluation board ? vga display adapter you need to provide the following items (see the appendix verified peripherals on page b-1 for a list of peripherals that are known to work with the lansc310 microcontroller evaluation board): ? an at-compatible 3.5" disk drive ? a standard 34-wire at disk-drive cable ? a vga monitor ? a cable to connect the vga monitor to the vga display adapter ? an at-compatible keyboard ? a standard pc power supply (at least 230 watts) ? a bootable 3.5" dos diskette evalbd.book : ch1 page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-4 1.0 board installation note: see lansc310 microcontroller evaluation board on page 2-2 for a layout diagram of the board. danger: make sure the power supply and the vga monitor are not plugged into an electrical outlet during the following steps. 1. remove the board from the shipping carton. visually inspect the board to verify that it was not damaged during shipment. the board contains several jumpers. the following steps assume all jumpers are in the factory default configuration. 2. inspect the 34-wire disk-drive cable that you are providing. the red wire along one edge of the ribbon cable indicates wire 1. connect one end of the 34-wire disk-drive cable to the disk drive just as you would for a standard pc installation. the disk-drive documentation should indicate where to put wire 1. connect the other end of the 34-wire disk-drive cable to the 34-pin connector p27 on the lansc310 microcontroller evaluation board with wire 1 toward the rom sockets. 3. insert the vga adapter into either of the isa slots on the lansc310 microcontroller evaluation board. the isa slots are labeled p21 and p22. 4. connect the vga monitor cable from the monitor to the d-connector at the end of the vga display adapter just as you would for a standard pc. 5. connect the keyboard to the keyboard connector at p10. 6. connect the connectors marked p8 and p9 from the standard pc power supply into the boards power connectors at p25 and p26. p8 connects to p25 (the six pins closest to the corner of the board); p9 to the other six pins. (see figure 2- 1 on page 2-2 for the connector locations.) make sure the black ground wires from p8 and p9 meet in the middle of the boards p25 and p26 connectors. danger: failure to verify and check the power supply connections may result in total destruction of the lansc310 microcontroller evaluation board. ! ! evalbd.book : ch1 page 4 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-5 1.0 7. find one of the 4-wire power connectors from the pc power supply and attach it to the 4-pin connector on the disk drive just as you would for a standard pc installation. the disk-drive documentation should indicate the proper orientation of the power cable. 8. insert the bootable dos diskette (not included) in the disk drive. 9. plug the vga monitor into an electrical outlet. 10. apply power to the lansc310 microcontroller evaluation board by connecting the pc power supply to an electrical outlet. if equipped, turn on the power-supply switch. the power supply fan should be operating. press the black micropower off button, sw5. the red led should now be lit. 11. press the red reset button, sw2. you should see the bios boot message on the monitor. when booting after being powered off, the cmos rom is not configured and you need to use the bios setup utility to configure the system. follow the instructions shown on the screen to enter the setup utility. once you are in the setup utility, you can set the systems processor speed, date, time, and other options (see systemsoft bios set-up screen options on page 2-6 or phoenixpico bios main menu setup screen options on page 2-11). 12. save and exit the setup utility. note: the evaluation board does not have a battery backup. you need to run the setup utility each time the system is powered off. 13. the system should now boot from the dos diskette just like a standard pc. evalbd.book : ch1 page 5 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-6 1.0 table 1-1. installation troubleshooting problem solution the boards power led does not light when the power supply is turned on. the black micropower off button, sw5, needs to be pressed after power-up. the boards power led does not light even after the micropower off button, sw5 is pressed. check power supply connections at p25 and p26. the red power led is on but i see nothing on the vga monitor and do not hear any beeps from the speaker nor hear the head synchronization on the disk drive. ensure processor reset by pressing the red reset button, sw2. i hear a beep on the speaker but see nothing on the vga monitor. check that the monitor has ac power. check that the monitor is correctly connected to the vga display adapter. check that the display adapter is correctly seated in the isa slot. i get the startup message on the monitor but it says theres a cmos checksum error and doesnt finish booting. this is the normal condition after power- up. the lansc310 microcontroller evaluation boards cmos ram does not have battery backup. follow the bios instructions to run the setup utility to configure the cmos ram. once configured, the cmos ram can be saved by leaving the power supply on but using the micropower off button, sw5, to power down the board. ive configured the cmos ram but i dont hear any sound from the disk drive and the system does not boot from the diskette. check that the 34-wire cable to the disk drive is properly connected at both the disk-drive end and the board end (board connector p27). check that the cmos setup indicates that drive a is a 3.5" 1.44 mbyte drive. i hear the diskette being accessed but get an error message "non system disk". check that the diskette in the drive is indeed bootable, just as you would on a standard pc. evalbd.book : ch1 page 6 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-7 1.0 connecting an ide hard drive this section describes how to connect an ide hard drive to the lansc310 microcontroller evaluation board. you need to provide the following additional items: ? an ide-compatible hard drive of size not more than 512 mbyte. see the appendix verified peripherals on page b-1 for a list of hard drives that are known to work. note that connor and fujitsu hard drives do not work with the lansc310 microcontroller evaluation board. ? a standard 40-wire at ide cable. assuming you have successfully booted to dos from a disk drive as described in booting dos from a diskette on page 1-2, do the following: 1. disconnect power by unplugging the pc power supply from the ac outlet. warning: if the pc power supply is on but the board has been put in a standby mode using the micropower off button, there is still some power on the board. completely unplug the power supply before continuing. 2. inspect the 40-wire ide cable that you are providing. the red wire along one edge of the ribbon cable indicates wire 1. connect one end of the 40-wire ide cable to the hard drive just as you would for a standard pc installation. the hard drive documentation should indicate where to put wire 1. connect the other end of the 40-wire ide cable to the 40-pin connector p28 on the lansc310 microcontroller evaluation board with wire 1 toward the rom sockets. i get a "missing keyboard" error message on the monitor during boot-up. check that keyboard is properly connected. there is a problem you cannot resolve. contact the amd technical support hotline at 1-800-222-9323. problem solution ! evalbd.book : ch1 page 7 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-8 1.0 3. find one of the 4-wire power connectors from the pc power supply and attach it to the 4-pin connector on the hard drive just as you would for a standard pc installation. the hard drive documentation should indicate the proper orientation of the power cable. 4. apply power to the lansc310 microcontroller evaluation board by connecting the pc power supply to an electrical outlet. then press the black micropower off button, sw5. the red led should now be lit. 5. press the red reset button, sw2. you should see the bios boot message on the monitor. when booting after a power-up, the cmos rom is not configured and you need to use the bios setup utility. follow the instructions shown on the monitor to enter the setup utility. 6. in the bios setup utility, you need to configure drive c for the proper number of heads, cylinders and sectors. (some bios products have an autodetect feature that automatically detects this information; some require you enter this information manually.) you should be able to get these numbers from your hard drive documentation. follow the prompts to save this configuration and exit the bios setup utility. 7. whether or not your hard drive contains an already installed bootable disk image (written from some other pc), you should still keep your bootable diskette in the a drive and boot from that. after you boot properly from a, try to do a directory listing of c. if the directory listing of c works, you can try removing the diskette from a and booting from c (ctrl-alt-delete). note that not all bios have the same mapping of logical to physical sectors on a hard drive, so if your hard drive was written by the bios on some other computer, it may not be readable by the bios on the lansc310 microcontroller evaluation board. if you are unable to boot from c, you should reformat the hard drive for use on the lansc310 microcontroller evaluation board (see your dos documentation for how to reformat your hard drive). evalbd.book : ch1 page 8 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-9 1.0 for more information ... if you need more information about: ? how to setup and use the serial ports or parallel port, including a serial mouse, see serial ports on page 2-21. ? how to setup and use the parallel port, see parallel port on page 2-21. ? how to add a ps/2 mouse, see ps/2 mouse on page 2-20. ? how to change the processor speed, see systemsoft bios on page 2-6 or phoenixpico bios on page 2-10. ? how to change the amount of dram, see dram main memory on page 2- 19. ? how to use a local bus card, see local bus mode on page 2-18. ? how to enable power management functions, see systemsoft bios on page 2-6 or phoenixpico bios on page 2-10. evalbd.book : ch1 page 9 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 1-10 1.0 evalbd.book : ch1 page 10 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual 2-1 chapter 2 board functional description the lansc310 microcontroller evaluation board provides a development platform for lansc310 microcontroller-based designs. read the following sections to learn more about the board: ? board layout on page 2-2 ? evaluation board restrictions on page 2-4 ? bios on page 2-5 ? bus modes on page 2-16 ? memory on page 2-18 ? i/o on page 2-20 ? roms on page 2-22 ? power measurement on page 2-23 ? power management on page 2-24 ? micropower off mode on page 2-26 see evaluation board setup summary on page a-1 for a summary of the board settings. see board layout suggestions on page c-1 for board layout strategy for the 32-khz oscillator, the plls, and the power supplies. evalbd.book : ch2 page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-2 1.0 board layout figure 2-1. lansc310 microcontroller evaluation board u17 u18 u19 u16 u50 cpu jp16 jp3 jp6 jp5 jp4 jp1 jp2 jp7 jp13 jp11 jp12 jp18 jp17 jp10 isa slots ide and floppy sw3 keyboard power connector 16c550 uart (super i/o) 16c450 uart ( lansc310) parallel port rp1Crp2 local bus card connector ps/2 mouse dram simm sockets reset suspend /resume sw4 u20 u59 jp32 jp29 jp31 jp25 u28 jp30 jp37 jp36 jp28 breadboard area micropower off mode system power on light kbd/mouse controller application roms bios roms high roms low roms even odd even odd national super i/o jp26 sw5 jp19 vcc1 vsys vmem avcc dram vcc vcc vcc5 vsys2 jp27 jp24 bank 0, low byte bank 1, high byte p21 p22 p45 p11 p10 p27 p28 p25 p19 p44 p1 p3 p2 p4 p24 sw2 sw1 bank 1, low byte bank 0, high byte 72-pin simm p5 p6 p7 p8 p9 rp5-rp6 p26 evalbd.book : ch2 page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-3 1.0 table 2-1. board layout part description page number jp1Cjp7 power measurement 2-23 jp10Cjp11 power measurement 2-23 jp12 rom type 2-22 jp13 application rom size 2-22 jp16 2x cpu clock 2-16 jp17 super i/o uart 2-16 jp18 ps/2 mouse 2-16, 2-20 jp19 power measurement 2-23 jp32 bios rom selection 2-5, 2-22 rp1Crp6 bus mode selection 2-16 sw1 suspend/resume sw2 reset sw3 local bus rdy config. 2-18 sw4-1 memory voltage setting 2-19 sw4-2 pirq1 connect 2-25 sw4-3 irq1 connect 2-25 sw4-4sw4-7 battery status 2-24 sw4-8 acin 2-25 sw5 micropower off mode 2-26 evalbd.book : ch2 page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-4 1.0 evaluation board restrictions ? the evaluation board isa bus can only run at 5 v. in normal designs this is not a restriction. ? the dram simm modules must have a 70-ns or less ras access time, for 33 mhz operation. ? the dram on the simm modules must be x4, x8 or x16. the lansc310 microcontroller cannot drive x1 dram due to the large capacitance associated with 32 loads. ? system dram population of both the 30-pin simm sockets and the 72-pin simm socket is not supported simultaneously. ? on the 72-pin simm socket, only 16-bit simm modules are fully supported. 32-bit simms can be used in the 72-pin simm socket but only half of the memory will be visible. ? software cannot be used to switch between isa and local bus configurations. one of the configurations must be set up before power-up. ? the bios rom sockets (u20 and u59) can only be populated with the following (the amd recommended part is also listed): C 128kx8 rom/eprom (amd 27c010) C 256kx8 rom/eprom (amd 27c020) C 128kx8 flash (amd 12-v 28f010 or 5-v 29f010) C 256kx8 flash (amd 12-v 28f020 or 28f020a) evalbd.book : ch2 page 4 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-5 1.0 ? application (dos) rom space is 16-bits wide (two or four devices must be used). ? the dos rom sockets (u16Cu19) can only be populated with the following (the amd recommended part is also listed): C 256kx8 rom/eprom (amd 27c020) C 512kx8 rom/eprom (amd 27c040) C 256kx8 flash (amd 12-v 28f020 or 28f020a) note: 512kx8 flash can be supported after a minor board rework. contact your amd fae for more information. ? some isa signals are not available when using local bus mode. refer to the lansc310 microcontroller data sheet and programmers reference manual for detailed information on the lansc310 functionality. ? the rtc ram (integrated in the lansc310 microcontroller)which is used to maintain time, date and system configuration datais cleared (lost) when power is removed from the v cc & av cc power planes. ? connectors are available to test local bus operation and modes. however due to bus loading, high speed operation is not possible without depopulating several components. bios the lansc310 microcontroller evaluation board comes with systemsoft bios programmed into the rom in socket u20, and phoenixpico bios programmed into the rom in socket u59. jumper jp32 selects which rom socket is used when the system boots (jp32 =1-2 selects socket u59, jp32=2-3 selects socket u20). each bios is an evaluation version specific to the evaluation board. an evaluation diskette for each bios is shipped with your kit. the bios rom images are located on their respective diskettes. note: these are evaluation bios only. each bios has been tested on the evaluation board and a list of know errata is available on the amd utilities diskette. for the most recent errata listing, contact your local amd representative. evalbd.book : ch2 page 5 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-6 1.0 systemsoft bios on system power-up, the systemsoft bios tests the system and determines if there are any problems with the setup configuration. since there is no cmos backup power on the evaluation board, it uses the default bios settings upon initial power- up. note: you need to run setup each time the system is powered off and on again. systemsoft bios also monitors the valid ram and time (vrt) bit in the rtc. this bit gets reset every time a hardware reset occurs. therefore, every time the system is reset using the red reset button, systemsoft bios flags a setup error. if this occurs, press f1 to continue booting with the previous setup information. if a setup error occurs, the bios prompts the user to press the cntl-alt-s keys to enter the setup screen. the setup screen can also be entered while in dos by pressing the cntl-alt-s keys. systemsoft has a familiar menu-driven setup screen. the options are listed in the table below. the default options are indicated in bold. table 2-2. systemsoft bios set-up screen options menu-bar item option description parameters standard set date sets system date (user enters) set time sets system time (user enters) diskette disk selects disk drive type 2.88mb 1.44mb (default for drive a) 1.7mb 720kb 360kb none (default for drive b) hard disk 1 sets parameters for hard drive 1 standard (select from list) custom (enter your own) auto (auto-detects drive pa- rameters; works for most drives) evalbd.book : ch2 page 6 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-7 1.0 hd1 translate parameters leave this unchecked hard disk 2 sets parameters for hard drive 2 standard (select from list) custom (enter your own) auto (auto-detects drive pa- rameters; works for most drives) hd2 translate parameters leave this unchecked internal com port sets the lansc310 inter- nal com port com1 com2 disabled super i/o com port sets the super i/o port com1 com2 com3 com4 disabled lpt port address sets parallel port base ad- dress 3bc 378 278 disabled video display sets video display type ega/vga cga80 cga40 monochrome cpu speed sets processor speed low 20mhz 25mhz 33mhz preferences numlock on turns on numlock on off fast boot when on, does not per- form memory check on off virus alter when on, alerts user of boot sector writes on off first boot selects which drive is booted from first drive a drive c menu-bar item option description parameters evalbd.book : ch2 page 7 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-8 1.0 typematic rate selects keyboard type- matic rate 10cps with 500ms delay boot password sets power-on password none scu password sets password to enter setup screen none memory video & bios shadow when on, shadows video and bios code to dram on off powermgmt enable powermgmt when on, sets up the lansc310 timers to tran- sition into low, doze and suspend power modes. when off, the lansc310 always runs at the cpu speed set in the stan- dard menu. on off idle amount of time the lansc310 remains in high speed mode with no activity prior to transi- tioning to low speed mode. off 0.5 seconds 1 seconds 2 seconds 4 seconds 8 seconds 12 seconds 16 seconds doze amount of time the lansc310 remains in low speed mode with no activity prior to transi- tioning to doze mode. off 5 seconds 10 seconds 20 seconds 30 seconds 40 seconds 50 seconds 60 seconds menu-bar item option description parameters evalbd.book : ch2 page 8 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-9 1.0 suspend amount of time the lansc310 remains in doze mode with no activ- ity prior to transitioning to sleep/suspend mode. off 2 minutes 4 minutes 6 minutes 8 minutes 10 minutes 12 minutes 14 minutes defaults defaults sets all setup screen set- tings to default values. n/a exit exit prompts the user to save the setup and reboot. n/a menu-bar item option description parameters evalbd.book : ch2 page 9 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-10 1.0 phoenixpico bios on system power-up, the phoenixpico bios tests the system and determines if there are any problems with the setup configuration. since the evaluation board does not have cmos back-up power, it uses the default bios settings on initial power-up. the user therefore needs to run setup each time the system is powered off and then on again. bios prompts the user to press f2 to enter setup mode and display the setup screen. bios uses the following keys for navigating the setup screens and editing or selecting options. four menus are available through the menu bar at the top of the window: ? main: use this menu for basic system configuration. ? advanced: use this menu to set the advanced features available on your systems chipset. ? power: use this menu to specify your settings for power management. ? exit: exits the current menu. the phoenixpico bios setup screen options for each menu are shown in the tables on the following pages. option defaults are indicated in bold. key function up arrow move cursor up down arrow move cursor down left arrow move cursor left right arrow move cursor right + or C toggle through options esc exit menu f1 help screen f9 setup defaults f10 previous values enter execute command evalbd.book : ch2 page 10 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-11 1.0 table 2-3. phoenixpico bios main menu setup screen options option description parameters system time hour, minute, and second (user enters) system date month, date, and year (user enters) diskette a diskette b selects the type of floppy disk drive(s) installed in your system. not installed (for b) 2.88mb/3.5" 1.44mb/3.5" (for a) 720kb/5.25" 1.2mb/5.25" 360kb/5.25" ide adapter master ide adapter slave ide adapters control the hard disk drive(s). the ide adapter supports one master drive and one optional slave drive. a separate sub-menu is used to configure each hard drive. not installed types 1C49* video system selects video type. ega/vga cga 80x25 monochrome evalbd.book : ch2 page 11 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-12 1.0 shadow options: video shadow memory shadow shadows video bios rom. shadows memory in the region specified. enabled disabled enabled disabled if enabled, options are: c800Ccbff cc00Ccfff d000Cd3ff d400Cd7ff d800Cdbff dc00Cdfff e000Ce3ff e400Ce7ff e800Cebff ec00Cefff boot sequence order in which the system searches drives for a boot disk. c: then a: c: only a: then c: embedded features: rom dos support enables booting from the rom dos image. enabled disabled rom/ram disk 0 non-magnetic boot device none serial rom/xms rom/ram disk 1 non-magnetic boot device none serial rom/xms option description parameters evalbd.book : ch2 page 12 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-13 1.0 * C if user type 48 is chosen, the following parameters must be set (they are usually found on the drive label): ? type number designation for the drive (user type = 48) ? cyl number of cylinders on specified drive (see drive label or documentation) ? hd number of heads on specified drive (see drive label or documentation) ? pre designates the starting cylinder of the read delay circuitry (set to 0) ? lz designates cylinder location where heads normally park when system is down (set to 0) ? sec number of sectors per track (see drive label or documentation) table 2-4. phoenixpico bios advanced menu setup screen options system memory amount of conventional memory detected during boot- up. n/a extended memory amount of extended memory installed on the system. it is detected automatically, so it should not require any manipulation. n/a option description parameters cpu speed advanced chipset control sets processor speed sets the divisor for the at clk. 9.2 mhz 20 mhz 25 mhz 33 mhz clk/6 clk/5 clk/4 clk/3 large disk access mode select "dos" if you have dos; select "other" if you use another operating system such as unix. dos other option description parameters evalbd.book : ch2 page 13 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-14 1.0 table 2-5. phoenixpico bios power menu setup screen options option description parameters power management mode turning this feature on enables power management. on off power savings selects power management mode. "max. battery life" and "max. performance" set power management options with predefined values. "customize" enables you to make your own selections. "disabled" turns off all power management. disabled customize max. battery life max. performance standby timeout sets inactivity period required to put the system in standby (partial power shutdown). disabled 1 sec 4 sec 8 sec 1 min 2 min 4 min 6 min 8 min 12 min 16 min suspend timeout sets inactivity period required after standby to suspend (maximum power shutdown). disabled 1 min 2 min 4 min 6 min 8 min 12 min 15 min 16 min evalbd.book : ch2 page 14 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-15 1.0 table 2-6. phoenixpico bios exit menu setup screen options fixed disk timeout sets inactivity period of fixed disk required before standby (motor off). disabled 10 sec 15 sec 30 sec 45 sec 1 min 2 min 4 min 8 min 12 min 16 min video timeout length of time either the keyboard or mouse remains inactive before the screen is turned off. disabled 10 sec 15 sec 30 sec 45 sec 1 min 2 min 4 min 8 min 12 min 16 min option description save changes & exit exit after writing all changed setup values to cmos. exit without saving changes exit without writing changed setup values to cmos. get default values load default values for all setup items. load previous values read previous values from cmos for all setup items. save changes write all setup item values to cmos. evalbd.book : ch2 page 15 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-16 1.0 bus modes the lansc310 microcontroller allows designs to utilize two different bus options: isa or local bus. while in isa mode, all of the devices isa bus signals are available (refer to the lansc310 microcontroller data sheet for a detailed description of the isa bus). local bus mode provides a 386 local bus in addition to a subset of isa bus signals. refer to the lansc310 microcontroller data sheet for a description of the signals available in each of these modes. the lansc310 microcontroller evaluation board allows testing in each of the two bus modes available from the lansc310 microcontroller. bus mode selection must be made before applying power to the board and cannot be changed while the board is in operation. selection of the bus mode is determined by the resistor packs labeled rp1, rp2, rp5, and rp6 (see table 2-7). when adjusting the bus mode jumpers, be sure to follow pin 1 designations . pin 1 on the resistor packs must correspond to pin 1 on the evaluation board. jp16Cjp18 must be set based on what bus mode is selected (see table 2-7). evalbd.book : ch2 page 16 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-17 1.0 table 2-7. bus mode selection and affected jumpers isa mode provided on the lansc310 microcontroller evaluation board are two physical 16- bit isa bus connectors. these slots are available for use when the board is configured for isa mode. the lansc310 microcontroller isa bus is a subset of a full isa bus. some signals are not available, therefore some isa cards may not function properly on the evaluation board (refer to the lansc310 microcontroller data sheet for a detailed description of the isa bus). the isa bus is wait-state programmable (refer to the lansc310 microcontroller programmers reference manual for details on programming isa bus timings). bus mode resistor pack setting jp16 jp17 jp18 1-2 2-3 1-2 2-3 open closed full isa install rp1 & rp2 only n/a n/a connects irq3 from super i/o n/a n/a connects irq12 from mouse local bus install rp5 & rp6 only 2x cpu clock n/a connects irq3 from super i/o n/a n/a connects irq12 from mouse evalbd.book : ch2 page 17 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-18 1.0 local bus mode the lansc310 microcontroller evaluation board provides a proprietary local-bus connector for testing of local-bus designs. since this connector is not standard, a custom interface is required to test the local-bus functionality of the lansc310 microcontroller on the evaluation board. in local bus mode, some of the isa bus signals are lost. refer to the lansc310 microcontroller data sheet for more details on what signals are available in this mode. since different local-bus implementations require different signal connections, the local bus signal vlrdyi can be connected to either vgardy (from the local bus device) or to vlrdyo (from the lansc310) using switches 2 and 3 on sw3 (switches 1 and 4 are no connects). note that vlrdyi corresponds to lrdy on the lansc310 microcontroller, and vlrdyo corresponds to cpurdy . note: due to loading, high speed operation is not possible without depopulating several components. memory the lansc310 microcontroller evaluation board supports up to 16 mbyte of memory in two different formats: 72-pin, 16-bit simm; or 30-pin, 8-bit simms. only one of these options can be used at a time. (that is, if the 30-pin dram sockets are used, the 72-pin dram socket must be empty. if the 72-pin dram socket is used, the 30-pin dram sockets must be empty.) sw3-2 affected signals on connects vgardy to vlrdyi off open sw3-3 affected signals on connects vlrdyo to vlrdyi off open evalbd.book : ch2 page 18 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-19 1.0 dram main memory the lansc310 microcontroller evaluation board comes standard with 2 mbyte of standard 30-pin, 70-ns dram simms installed on the board. the evaluation board requires drams with access times of 70 ns or less (for 33 mhz operation). the dram memory can be upgraded using 30-pin simms with 4- or 8-bit drams; simms with 1-bit drams cannot be used on the evaluation board due to loading restrictions associated with 32 loads. 16 mbyte of main dram memory can also be installed using a 72-pin, 16-bit simm module. this can be installed in the 72-pin simm socket located next to main memory bank 1 on the evaluation board (see figure 2-1 on page 2-2). on the 72-pin simm socket, only 16-bit simm modules are fully supported. 32-bit simms can be used in the 72-pin simm socket but only half of the memory will be visible. bios automatically detects the amount of dram installed. memory voltage setting the lansc310 microcontroller evaluation board allows system memory to operate at either 5 v or 3.3 v. when operating in local bus mode, 3.3 v memory must be used. in order to operate memory at 3.3 v, ensure that the memory is rated for 3.3-v operation. sw4-1 controls the voltage for the system memory. total memory bank 0 bank 1 1 mbyte two 512-kbyte empty 2 mbyte two 512-kbyte two 512-kbyte 2 mbyte two 1-mbyte empty 4 mbyte two 1-mbyte two 1-mbyte 8 mbyte two 4-mbyte empty 16 mbyte two 4-mbyte two 4-mbyte sw4-1 setting memory v cc off 3.3 v on 5 v evalbd.book : ch2 page 19 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-20 1.0 i/o the lansc310 microcontroller integrates several standard i/o interfaces. a 16c450-compatible uart, bidirectional parallel port is controlled by the lansc310 microcontroller. in addition, the lansc310 microcontroller evaluation board contains a super i/o, which contains a 16c550 uart, a floppy disk controller, and ide hard drive interface. a standard 9-pin connector is provided for an extended pc keyboard. a ps/2 port is provided for use with a ps/2 style mouse. both the keyboard and ps/2 mouse are driven by the 8042. ps/2 mouse a ps/2 port has been provided on the evaluation board for a ps/2-style mouse. this device is driven by the 8042 keyboard controller. while in isa or local bus mode, the lansc310 microcontroller irq12 signal is connected to the irq12 signal on the 8042 to control the ps/2 mouse. (see the settings for jp17 and jp18 in the table below.) bus mode jp17 jp18 1-2 2-3 full isa enables super i/o serial port irq do not use closed to enable ps/2 mouse irq local bus enables super i/o serial port irq do not use closed to enable ps/2 mouse irq evalbd.book : ch2 page 20 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-21 1.0 serial ports the evaluation board has two serial ports. connector p19 is connected to the lansc310 internal 16c450-compatible uart. connector p45 is connected to the super i/o 16c550 uart. the bios determines how the uart is set up, e.g., systemsoft bios allows the lansc310 to be set up as com1, com2, or disabled; and the super i/o uart as com1, com2, com3, com4, or disabled. (note that when the super i/o uart is configured as com1 or com3, the irq4 line from the super i/o is not connected, therefore polling must be used.) after dos is booted, the dos utility evalset.exe provided on the amd utilities diskette included in your kit can be used to reinitialize either uart to the desired configuration. refer to the documentation on the diskette for how to do this. parallel port connector p20 is connected to the lansc310 parallel port. most bios let you configure the parallel-port base address in the set-up screen. ide hard drive the lansc310 microcontroller evaluation board contains a standard 40-pin connection for an ide drive at location p28 (see the figure on page 2-2). pin 1 is at the end near the rom sockets. see connecting an ide hard drive on page 1-7 for a step-by-step guide. evalbd.book : ch2 page 21 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-22 1.0 roms the lansc310 microcontroller evaluation board provides two bios rom sockets and four application rom sockets capable of handling up to 256 kbyte of bios rom and up to 2 mbyte of application rom. the evaluation board supports bios and application roms as either flash or eprom devices. jp12 must be set to select either flash or eprom devices. two bios rom sockets, u59 and u20, are available on the evaluation board. each bios rom socket is capable of supporting 128-kbyte or 256-kbyte flash or eprom bios roms. the active bios rom is selectable by jp32. four 8-bit application rom sockets, u16Cu19, are provided on the evaluation board for rom-based applications such as rom-dos. u16 (even) and u17 (odd) make up one logical 16-bit rom (low) beginning at offset 0 in application rom space. u18 (even) and u19 (odd) make up a second logical 16-bit rom (high) beginning where u16 and u17 end in application rom space. these sockets can be populated with either 256 kbyte 8-bit flash, or 256 kbyte or 512 kbyte 8-bit eprom devices. jp13 selects the size of application roms that can be used. note: 512kx8 flash can be supported after a minor board rework. contact your local amd or distributor field application engineer for more information. jp12 type of rom 1-2 flash 2-3 eprom jp32 bios rom selection 1-2 u59 (phoenix) 2-3 u20 (systemsoft) jp13 application rom size 1-2 256kx8 (flash or eprom) 2-3 512kx8 (eprom only) evalbd.book : ch2 page 22 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-23 1.0 power measurement the evaluation board allows for measurement of current flow in separate v cc planes for power budget analysis. the following table summarizes the connections to the v cc jumpers. be sure to turn off system power before removing jp1C jp11. replace jp1Cjp11 before power-up or the system will not work. a dos application program has been provided to aid in placing the system in the various power management modes for power measurement. elanpmu.exe is on the amd utilities diskette included with your kit. see elan pmu evaluation utility on page 3-4 for more information on elanpmu.exe . jumper v cc logic connected to v cc plane jp1 v cc lansc310 core v cc only. always 3.3 v. jp2 v cc3 lansc310 av cc pin. analog v cc . always 3.3 v. jp3 v cc5 lansc310 v cc5 pin. diode clamp refs except v cc mem and av cc source pins. always 5 v except in full 3.3- v designs. (evaluation board limits to 5 v.) jp4 v ccmem lansc310 memory interface v cc . see the sw4 table on page 2-19 for 3.3-v or 5-v setting. restrictions do apply. also the diode clamp ref for pins sourced by the v ccmem pin. jp5 v ccsys lansc310 isa bus v cc and other misc. pins. 5 v or 3.3 v. refer to datasheet for details. jp6 v ccsys2 lansc310 alternate pin v cc . 5 v or 3.3 v. refer to datasheet for details. jp7 v ccmem53 system dram v cc plane. jp10 v cckbos 8042 v cc jp11 v ccrom bios and application rom v cc jp19 v cc1 lansc310 v cc1 pin 176. 5 v or 3.3 v. evalbd.book : ch2 page 23 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-24 1.0 bl1Cbl4 pins these signals are used to indicate the current status of the battery to the lansc310 microcontroller. a high signal indicates normal operating conditions, while a low indicates a warning condition. access to these signals has been provided on the evaluation board to allow designers to test their functionality. switches 4C7 on sw4 allow the bl1 Cbl4 signals to be toggles between gnd (warning) and 5 v (normal). breadboard area a breadboard area has been provided on the lansc310 microcontroller evaluation board. this area can be used as a convenient place to build custom circuits to interface to the evaluation board. the pins in this breadboard are all isolated from other pins and the rest of the board. power management the lansc310 microcontroller offers unparalleled power management in its class. in addition to low operating current, six power management modes are available: high speed, low speed, doze, sleep, suspend, and off. refer to the lansc310 microcontroller data sheet and programmers reference manual for an in-depth discussion of these modes. sw4 switches signal on off 4 bl1 gnd 5 v 5 bl2 gnd 5 v 6 bl3 gnd 5 v 7 bl4 gnd 5 v evalbd.book : ch2 page 24 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-25 1.0 suspend/resume the lansc310 microcontroller evaluation board provides a hardware option to allow the user to toggle between the high speed and suspend modes. by pressing the suspend/resume button after the system has powered up, the system enters the suspend mode (assuming the acin signal is low). by pressing the suspend/ resume button again, the system returns to high speed mode. the behavior of the system in suspend mode depends on the bios. power management simulation battery backup conditions can be simulated on the evaluation board by controlling the acin signal to the lansc310 microcontroller. when acin is low, power management functions on the lansc310 microcontroller are enabled. when acin is high, power management functions on the lansc310 microcontroller are disabled. switch 8 on sw4 controls the acin pin on the lansc310, allowing power management functions to take effect if they are enabled. in order to get true power measurements while in suspend mode, irq1 and pirq1 must be disconnected from the lansc310 microcontroller. the lansc310 microcontroller drives these signals low during suspend mode. since the peripherals connected to these lines drive them high, this creates the appearance of additional power drain. these signals can be easily disconnected while in suspend mode using switches 2 and 3 on sw4. before exiting from suspend mode, irq1 and pirq1 must be reconnected for the system to function properly. sw4-8 acin on gnd off 5 v sw4-2 pirq1 on connect off disconnect sw4-3 irq1 on connect off disconnect evalbd.book : ch2 page 25 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 2-26 1.0 micropower off mode this mode is the lowest power mode for the lansc310 microcontroller. when the system is initially powered by turning on the power supply and then pressing the micropower off button, sw5, the system enters high speed mode. the red power light indicates that the system is fully powered on. pressing the micropower off button, sw5, again, causes the lansc310 microcontroller to enter micropower off mode. during micropower off mode, only av cc , v cc , and the 32-khz crystal remain active. the system is essentially off, but the rtc remains in operation. please refer to the lansc310 microcontroller data sheet for a more detailed explanation of this feature. evalbd.book : ch2 page 26 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual 3-1 chapter 3 using the software the lansc310 microcontroller evaluation board kit currently ships with four diskettes: the systemsoft evaluation diskette, the phoneixpico evaluation diskette, the datalight software evaluation kit diskette, and the amd utilities diskette. systemsoft evaluation diskette this diskette contains the evaluation version of systemsofts bios rom image programmed into the rom on the evaluation board. please refer to the documentation on the diskette for further information about these files. phoenixpico evaluation diskette this diskette contains the evaluation version of the phoenixpico bios rom image programmed into the rom on the evaluation board. please refer to the documentation on the diskette for further information about these files. datalight software evaluation kit diskette this diskette contains software for evaluating datalights rom-dos and winlight software on the evaluation board. please refer to the documentation on the diskette for further information about these files. evalbd.book : ch3 page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-2 1.0 amd utilities diskette this diskette contains several utilities developed specifically for the evaluation board to assist the user in their evaluation and design with the lansc310 microcontroller. some of these utilities may work on other lansc310 microcontroller-based platforms, but their functionality outside of the evaluation board cannot be guaranteed and therefore is not supported. the following utilities are included on the amd utilities diskette: elaninit.zip initialization example for the lansc310. elanpmu.zip utility for demonstrating the lansc310 power- management features. evalset.zip utility to configure the two serial ports on the evaluation board. source code is provided. flash.zip utility for flashing amds 12-v 28f010, 5-v 29f010, 12-v 28f020, or 12-v 28f020a flash parts on the evaluation board. source code is provided. mmsinfo.zip utility for displaying mms window configuration information. source code is provided. mmsview.zip utility for viewing data through the mmsa pages. regdump.exe utility for displaying the lansc310 registers. sdb.zip simple, debug utility for command-line accesses to lansc310 registers. elaninit.zip this zipfile contains assembly language routines that give an example of how to initialize the lansc310 microcontroller registers, enable dram, handle smi events, and report status through the serial port. the unzipped files compile to form a binary image that can be programmed into a rom and placed in the bios rom socket. refer to the readme and *.txt files in this zipfile for more information. evalbd.book : ch3 page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-3 1.0 elanpmu.zip this zipfile contains elanpmu.exe , which can be used to place the lansc310 microcontroller into various pmu modes. it allows the user to modify certain settings for each pmu mode. the user can then measure current consumption of the lansc310 microcontroller cores and see how the current changes, depending on the current settings and pmu mode. refer to elan pmu evaluation utility on page 3-4 for more information. evalset.zip this zipfile contains evalset.exe , which has been provided to allow easy activation of the serial and parallel ports on the lansc310 microcontroller evaluation board. the bios on this board was designed to be generic, therefore these functions are not enabled by the bios on the evaluation board. this utility can be used to set up the base addresses for serial port 1, serial port 2 and parallel port 1 on the evaluation board. for complete operating instructions on evalset.exe , refer to evalset serial and parallel port setup utility on page 3-10. flash.zip this zipfile contains flash.exe , which can be used to program 28f010, 29f010, 28f020, and 28f020a flash parts on the lansc310 microcontroller evaluation board. source code is provided for this utility to be able to modify it for other platforms and other amd flash devices. refer to the readme and *.txt files in this zipfile for more information. mmsinfo.zip this zipfile contains mmsinfo.exe , a utility for displaying the current status of the mmsa and mmsb windows. if an mms window is enabled, then information for each page within the window is displayed. if an mms window is disabled, then the information on each page within the window is not displayed. source code for this utility is also provided. the source code contains routines that show how to manipulate the lansc310 microcontrollers mms window registers. refer to the readme and *.txt files in this zipfile for more information. evalbd.book : ch3 page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-4 1.0 mmsview.zip this zipfile contains mmsview.exe , which is a dos application that may be used to inspect various resources that are accessible by the lansc310 microcontroller mms subsystem. these resources include system ram, the bios rom (or resources accessed by the romcs signal), or the dos rom (or resources accessed by the doscs signal). for complete operating instructions on mmsview.exe , refer to memory management system (mms) viewer utility on page 3-12. regdump.exe this register dump utility has been provided for use on the lansc310 microcontroller evaluation board. it is intended to provide a user with an easy-to- use register manipulation program. this program displays the index register in the lansc310 microcontroller, grouped by functionality. for complete operating instructions on regdump.exe , refer to register dump utility on page 3-19. sdb.zip this zipfile contains sdb.exe , a simple debug utility useful when working with the lansc310 microcontroller. it allows the user to easily access the lansc310 microcontrollers index registers, and i/o ports from the command line. this way the user can place several sdb command lines in a batch file and just execute the batch file. source code is provided. refer to the readme and *.txt files in this zipfile for more information. elan pmu evaluation utility the elan pmu evaluation utility is a dos utility designed to demonstrate the power management capabilities of the lansc310 microcontroller. this utility only runs on rev. 2.2 or later of the lansc310 microcontroller evaluation board (the revision number is silkscreened on the board next to the amd logo and name). by using a current meter attached to the lansc310 microcontrollers various voltage plains, the user can see how different pmu setups affect power consumption. it is recommended that the user read through the lansc310 microcontroller programmers reference manual to gain an understanding of the lansc310 microcontrollers power management functions. to bring up the main menu, type the following at the dos prompt: elanpmu evalbd.book : ch3 page 4 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-5 1.0 the following main menu appears: elan pmu evaluation utility version 1.0 a: setup pmu mode characteristics (pmcx pins, cpu speed) b: force pmu state transitions c: test battery level & acin pins x: restore pmu state and exit to dos z: leave current pmu values and exit to dos enter selection =>/ the spinning cursor "/" is used to emulate typical cpu activity. this activity gives a lower current reading for core lansc310 microcontroller current than if the processor was sitting idle waiting for keyboard input. this is because cycles to the isa devices (which occur as a result of this activity) are run at 9.2 mhz. cpu idle cycles occur at the high speed pll mode frequency (33/25/20/9.2 mhz). a: setup pmu mode characteristics (pmcx pins, cpu speed) this menu selection brings up a matrix of options that can be set for each pmu mode. the value of the highlighted matrix item can be changed by pressing the "+" or "C" keys on the keyboard. the arrow keys control which item is highlighted. matrix items with a "*" after them are fixed in the lansc310 microcontroller and cannot be highlighted or changed. matrix items with a "#" after them are fixed at the current state due to a requirement of the evaluation board. these items cannot be highlighted or changed. changes made to this screen do not take effect until either the "s" key is pressed (program elan), or the "x" key is pressed (program elan & return to main menu). to exit this screen without programming the lansc310 microcontroller with any changes, press the "q" key. to restore the values to those currently programmed in the lansc310 microcontroller, press the "l" key. while in this screen, the cpu is running in high speed pll mode. when any changes to the high speed pll mode column are saved, the results are immediately noticeable (e.g., the effect cpu speed has on core current). changes to other columns on the screen are not noticeable until those pmu modes are entered. evalbd.book : ch3 page 5 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-6 1.0 the state of the pmc pins can be set for each pmu mode. while the particular state the pmc pin is in does not significantly affect the lansc310 microcontrollers power consumption, this matrix allows the user to see what control the user has for external control of the pmc pins for each pmu mode. note that the pmc pin setting for the low and high speed pll modes mirror each other. changing the value in one column causes the value in the other column to change also. high speed pll mode column ? the cpu speed can be set to 33 mhz, 25 mhz, 20 mhz, or 9.2 mhz. ? both the high speed and low speed plls for this mode are enabled. ? the state of the pmc pins for this mode mirror the settings in low speed pll mode. changing the state in this mode also changes the state for low speed pll mode. ? auto low speed mode, when enabled, switches the cpu clock speed to operate at 9.2 mhz for the duration of time listed in als duration matrix item (0.25, 0.50, 1.0, 2.0 seconds). this switch is triggered at a rate determined by the als trigger matrix item, which can be set to 4, 8, 16, or 32 seconds. the als trigger period and als duration time are stored in write-only registers. therefore it is not possible to read the current lansc310 programed value when this utility is started. the default values of 4 seconds for the als trigger and 0.25 seconds for the als duration are programmed at start-up time. ? the cpu idle speed can be set to "high" or "low." "high" means that during idle cycles the cpu runs at the current high speed cpu speed (33, 25, 20, or 9.2 mhz); "low" means 9.2 mhz. the cpu idle speed can only be set "low" if the high speed cpu is set to 20 mhz or 9.2 mhz. if the high speed cpu speed is set to 33 mhz or 25 mhz and the cpu idle speed is then set to "low", the cpu speed changes to 20 mhz. similarly, if the cpu idle speed is set to "low" and the high speed cpu speed is changed to 33 mhz or 25 mhz, the cpu idle speed is changed to "high." evalbd.book : ch3 page 6 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-7 1.0 low speed pll mode column ? the cpu speed can be set to 4.61 mhz, 2.30 mhz, 1.15 mhz, or 0.58 mhz. ? the high speed pll can be enabled or disabled in this mode. ? the low speed pll is always enabled for this mode. ? the state of the pmc pins for this mode mirror the setting in high speed pll mode. changing the state in this mode also changes the state for high speed pll mode. doze mode column ? the cpu for this mode can be turned "off," or it can be enabled to run at 9.2 mhz in response to irq0 being generated. "irq0-9.2mhz" appears as the matrix item. for this mode, the cpu only runs at 9.2 mhz during the time irq0 is being processed. setting this matrix item to "irq0+64 r" enables the cpu to run at 9.2 mhz while processing irq0 and the cpu remains running for 64 refresh cycles after irq0 processing is completed. ? the high speed pll is always disabled for this mode. ? the low speed pll and video pll (controlled by the same bit) can be enabled or disabled for this mode. sleep mode column ? the cpu is always off in this mode. ? the high speed pll is always off in this mode. ? the low speed pll and video pll (controlled by the same bit) can be enabled or disabled for this mode. suspend & off mode column ? the cpu is always off in these modes. ? the high speed pll is always off in these modes. ? the low speed pll and video pll (controlled by the same bit) can be enabled or disabled for these modes. evalbd.book : ch3 page 7 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-8 1.0 b: force pmu state transitions elan pmu evaluation utility force pmu modes a: force pmu to low speed pll mode xxx mhz b: force pmu to doze mode c: force pmu to sleep mode d: force pmu to suspend mode x: return to main menu enter selection=>/ below this menu, the current pmu mode that the lansc310 microcontroller is in is displayed along with any options set using option a from the main menu. for modes where the cpu clock is running, the spinning activity cursor "/" helps show the speed of the cpu. a: force pmu to low speed pll mode xxx mhz ? the cpu clock slows to the speed shown. ? if set up to do so, the high speed pll is shut off. ? pressing any key or toggling the acin pin brings the system back to high speed pll mode. b: force pmu to doze mode ? if the cpu clock speed is off, no spinning activity cursor is displayed. ? if the cpu clock is enabled for irq0 processing only, then the spinning activity cursor transitions about once every 10 seconds. ? if the cpu clock is enabled for irq0+64 refresh cycles, then the spinning activity cursor spins. ? pressing any key or toggling the acin pin brings the system back to high speed pll mode. c: force pmu to sleep mode ? the keyboard is disabled in this mode. pressing the suspend/resume key or toggling the acin pin returns the system to high speed pll mode. evalbd.book : ch3 page 8 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-9 1.0 d: force pmu to suspend mode ? the keyboard is disabled in this mode. pressing the suspend/resume key or toggling the acin pin returns the system to high speed pll mode. c: test battery level & acin pins this menu item shows how the battery level and acin pins are tied to the pmu. pin bl1 can be used to force the cpu to run at 9.2 mhz. pin bl2 can be used to transition the pmu into sleep mode. pin bl4 can be used to transition the pmu into suspend mode. each of the above transitions can be enabled or disabled by selecting item "a: change bl transition masks", highlighting the appropriate field, and using the "+" and "C" keys to enable or disable the transitions. there is also an option to enable/disable a transition message. if enabled, a transition message is displayed as the lansc310 microcontroller transitions from low speed to doze mode, prompting the user to press a key before the system transitions to sleep or suspend mode. the box on the top right of the screen displays the current state of the bl and acin pins. status for the bl4 pin is not directly readable by the lansc310. on the lansc310 microcontroller evaluation board, the state of the bl pins and acin pins are controlled by the red 8 bank dip switch sw4. switches 4C7=bl1 Cbl4 ; switch 8=acin. acin must be set to 0 in order for any of the bl pins to cause a pmu state change. once a bl pin is used to cause a pmu state change, setting acin to 1 (active) wakes up the system and returns the pmu to high speed pll mode. x: restore pmu state and exit to dos this option restores the lansc310 microcontrollers index registers to the value they were set to when the program was entered, and returns the user to the dos prompt. z: leave current pmu values and exit to dos this option leaves the lansc310 microcontrollers index registers set at their current value, and returns the user to the dos prompt. evalbd.book : ch3 page 9 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-10 1.0 evalset serial and parallel port setup utility evalset.exe has been provided to allow easy activation of the serial and parallel ports on the lansc310 microcontroller evaluation board. the bios on this board was designed to be generic, therefore these functions are not enabled by the bios on the evaluation board. this utility can be used to set up the base addresses for serial port 1, serial port 2 and parallel port 1 on the evaluation board. serial port 1 serial port 1 is the 16c450 uart internal to the lansc310 microcontroller. its base address can be set to either 3f8h or 2f8h. the irq level can be set to either 3 or 4. if you enter a base address of 0, the internal uart is disabled. if you enter a valid base address but an irq of 0, then the uart is enabled but it is not attached to an interrupt line. examples evalset ser1 0x3f8 4 sets the internal uart to be com1: evalset ser1 0x2f8 3 sets the internal uart to be com2: evalset ser1 0 0 disables the internal uart note: once the base address is set, the uart is programmed to 9600 baud, no parity, 8 data, 1 stop. serial port 2 serial port 2 is connected to the 16c550 uart1 of the super i/o chip (uart2 is not connected). its base address can be set according to the table below. note that if you want serial port 2 to generate an interrupt, only irq3 can be used. this is because irq4 from the super i/o is not connected. however, the base addresses that are associated with an irq4 configuration can still be set as long as the port is used in polled mode. irq base addresses 3 2f8, 2e8, 238, 2e0, 228 4 (polled only) 3f8, 3e8, 338, 2e8, 220 evalbd.book : ch3 page 10 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-11 1.0 examples evalset ser2 0x2f8 3 sets the super i/o uart to be com2: evalset ser2 0 0 disables the super i/o uart note: once the base address is set, the uart is programmed to 9600 baud, no parity, 8 data, 1 stop. parallel port 1 this is the internal parallel port on the lansc310 microcontroller. the parallel port base address is controlled through the bus configuration registers (see the lansc310 microcontroller programmer's reference manual ). these bus configuration registers can only be programmed before isa or local bus accesses are made, so setting the parallel port base address or disabling the parallel port can only be done at boot time. thus, the evalset utility merely allows control of the epp and bidirectional modes on the parallel port. any base address that is specified is ignored by the evalset utility. examples evalset par1 0x3b8 epp_on bi_on turns on epp and bidirectional modes. evalset par1 0x3b8 epp_off bi_off turns off epp and bidirectional modes. usage evalset.exe can be called from the dos prompt, autoexec.bat file, or config.sys file with the proper parameters. config.sys example install=evalset.exe ser1 0x3f8 4 install=evalset.exe ser2 0x2f8 3 install=evalset.exe par1 0x3b8 epp_off bi_on evalbd.book : ch3 page 11 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-12 1.0 memory management system (mms) viewer utility this utility is part of the collateral for the lansc310 microcontroller. the lansc310 microcontroller is a highly integrated device with many subsystems. many of these subsystems are unique to the lansc310. the purpose of the mmsview utility is to provide the new lansc310 microcontroller user with the ability to explore the capabilities of the lansc310 mms subsystem without having to invest much in the way of software development or chip register learning time. description mmsview is a dos application that may be used to inspect various resources that are accessible by the lansc310 mms subsystem. these resources include system ram, the bios rom (or resources accessed by the romcs signal), or the dos rom (or resources accessed by the doscs signal). with this utility, the following operations may be performed: ? directly display any region of the system ram (0C16 mbyte range), bios rom (0C16 mbyte range), and dos rom (0C16 mbyte range). ? step forward or backward through the data in 256-byte steps or 16-kbyte steps. ? select any lansc310 mms page from mmsa to view system resources through. ? fill areas of system ram memory with a selected byte. ? append the currently displayed page of data to a log file in either ascii or binary formats. ? view dos rom using an 8- or 16-bit interface. ? perform continuous read/compare operations from a selected resource, and indicate miscompares on the display. evalbd.book : ch3 page 12 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-13 1.0 scope mmsview is provided to enable discovery and understanding of the capabilities of the lansc310 microcontroller mms system. it has other uses such as looking at dos rom disks to ensure that the odd/even parts are placed in the sockets correctly. it is not designed to be a comprehensive or automated diagnostic program, although its use may help in the debug of certain problems. mmsview uses mmsa only. to retain compatibility with systems using vga video, mmsb was left outside the scope of this tool. it was designed on, tested on, and meant for use on the lansc310 microcontroller evaluation board revision 2.2 or later. the fact that it may run on other customer platforms is purely coincidental note: no support of any kind is provided for porting this utility to any platform other than the lansc310 microcontroller evaluation board revision 2.2 or later except by special agreement between amd and the customer. operating instructions command-line parameters mmsview assumes that mms page 4 (resides at d0000h when mms page 0 is set up to reside at c0000h) is available for use. this default may be overridden using a command-line parameter as shown below. syntax: mmsview [ page ] where: page is a number from 0C7 to indicate the initial mms page to view the system resources through. if an invalid command-line parameter is detected (not a number, out of range, etc.) the default mms page (4) is used. this option is provided to allow resolution of system address space conflicts that may occur when using this program while some other driver is loaded (emm386, etc.). there are no other command-line parameters available. evalbd.book : ch3 page 13 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-14 1.0 initial state after mmsview has been invoked from the dos command line, data is displayed in a fashion similar to dos debug. mmsa page 4 at d0000h is selected, and the device that is accessed is system ram. the first 256 bytes of the selected device are displayed starting at offset 0 (i.e., the start of the interrupt vector table at 0:0 in ram.) keystroke commands keystroke commands are invoked by simply pressing the keys noted below. whenever a keystroke command requires user input, prompts request the required data. if a command that requires user input is to be aborted without invoking the command, press the escape key, and the main data display returns. a command summary follows. ? pressing the question-mark key from the main data-display screen displays a quick help list of the keystroke commands available to the utility. press the space bar from the quick help screen to return to the normal main display screen. + the plus key moves forward through the data 256 bytes at a time. the plus key thus makes it simple to view the next 100h bytes of data on the selected device. C the minus key performs the inverse operation of the plus key, and causes the previous 256 bytes of device data to be displayed. the program disallows negative addresses, and gives a warning click from the speaker if you press the minus key when the first address displayed on the screen is 0. home key the home key displays the data at offset 0 on the current device. escape the escape key causes the utility to return control to the dos prompt. note that no cleanup is done as the program exits, so it is recommended that the user cold boot before performing any other important operations, especially if romdos or emm386 drivers were loaded on the system when mmsview was invoked. evalbd.book : ch3 page 14 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-15 1.0 page up the page up key displays data on the previous 16-kbyte boundary. for example, if the current device data starting at offset 4100h is being displayed, and page up is pressed, the data from device offset 0100h is displayed. page down the page down key does the inverse of the page up key; it displays data from the next 16-kbyte boundary. space bar the space bar (or any key besides the other command keys listed in this section) simply rereads the data from the selected resource, and refreshes the main data display screen. the main data screen does not constantly update normally. press the space bar (or any other non-command key as specified in this list) to refresh the screen with the new data. for a continuous read mode, see the c command below. a this key is only useful on boards with pcmcia. c the c key is useful for detecting changes in reading the data from a given resource. an example application for this feature is in the detection of timing problems (incorrect wait-state setup, etc.). when you press the c key, a snapshot of the current device data is taken, and stored into a local buffer. after this, continuous reads of the current device data are compared to the buffer. miscompares cause the offending byte location to flash, and the result of an exclusive or between the buffer (snapshot) and the current device data is displayed. this allows bit errors to be picked out easily. upon leaving continuous read/compare mode, the blink attribute is removed from the characters for easier reading of the resulting data. the bytes which have the bit miscompares are left highlighted in white (versus light gray for the normal data). any new command which causes the data to be read from the device again removes the highlight attribute from the displayed data completely. if the highlight attribute needs to be removed without losing the bit error data which may have been captured, the r command may be used (see below). evalbd.book : ch3 page 15 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-16 1.0 d the d key selects which device the current mms page points to. pressing the d key causes the system to prompt for the new device. enter a 0, 1, or 3 (0 = dos rom, 1 = system ram, 3 = bios rom), and press enter. invalid input is not accepted. once a new device has been entered, the main data display returns showing the data read from the selected device at the current offset . for example, if you are looking at the dos rom at offset 4000h, and you use the d command to select the bios rom, the data displayed is from offset 4000h of the bios rom. f the f command allows a range of memory to be filled with a user-selectable byte. pressing the f command brings up prompts for the start and stop fill addresses, and requests the fill byte. fill operations are available only when ram is the selected device. this command does not know how to write to flash devices in a dos rom socket. g the g command allows you to go to any place in the memory map desired. it is the random access equivalent to the plus and minus keys. it provides one additional benefit in that the data byte which resides at the address specified by the user to go to is highlighted for easy recognition. i the i key allows the dos rom interface to be toggled between the 8- and 16-bit interfaces supported on the lansc310 microcontroller. this is useful if running the utility on a hardware platform that has an 8-bit dos rom interface as opposed to the 16-bit dos rom interface on the lansc310 microcontroller evaluation board. l the l command allows one screens worth of data to be appended to a log. successive screens can be captured to the same file in this manner. pressing the l command prompts the user as to whether the output file should be a binary image of the data, or whether a dos debug-like ascii representation should be saved. if the binary option is chosen, data is logged to a file named mmsview.bin . if the ascii option is selected, the output file is mmsview.asc . evalbd.book : ch3 page 16 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-17 1.0 n the n command allows the user to select the use of a new mms page (0C7). this can be useful in avoiding system conflicts. the default page can be changed before entering the program using the command-line capability to set this option as described on page 3-13. p the p command is essentially a g command that accepts its input in terms of 16k pages. in other words, you can randomly access data on specific 16-kbyte boundaries using this command. for example, if you want to view the start of the first 16-kbyte boundary of a device, select the p command, and input 0 when prompted to specify page 0. this can be done just as easily using the g command and supplying an address thats a multiple of 4000h. r the r command resets the miscompare indicators as explained earlier in the section that explains the c command. see the c command on page 3-15 for more detail. s this key is only useful on boards with pcmcia. restrictions on use although designed for the lansc310 microcontroller evaluation board, this utility may work on other vendors platforms. (however, its functionality outside of the lansc310 microcontroller evaluation board cannot be guaranteed and therefore is not supported.) there are two key elements for compatibility: 1. mmsview assumes that mmsa is programmed to begin page 0 at c0000h. the starting location of mmsa is not reset by the utility in an attempt to maintain software compatibility with customer platforms as this would probably cause the customers platform to crash. use this utility on a customer platform only if customer-platform initialization programs mmsa page 0 to start at c0000h. evalbd.book : ch3 page 17 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-18 1.0 2. the second element of compatibility is the use of the mms windows on the customer platform. mmsview assumes that mms page 4 (resides at d0000h when mms page 0 is set up to reside at c0000h) is available for use. this may conflict with drivers loaded on the evaluation board platform that require the use of mms (romdos, emm386, etc.). it may also conflict with customer resources located on customer platforms. see operating instructions on page 3-13 for details on how to change mms windows. it is recommended that the test platform/evaluation system be cold booted (using reset button) after mmsview exits so that the lansc310 microcontroller setup registers are restored to the proper values before doing further work on the platform. this is required not only on customer platforms, but on any lansc310 microcontroller evaluation board that has any romdos, emm386, or other drivers installed that require use of the mms, or memory regions that are controlled by the mms. again, mmsview makes no attempt to restore the system to its initial state: reset the system when finished . use caution when selecting the mms page to use. selecting a page that causes conflicts with other system resources can lock the system. for example, using a vga card in the isa slot of the evaluation board, and selecting pages 0 or 1 of mmsa causes system conflicts since vga bios decodes at c0000h for 32 kbyte, and mmsa pages 0 and 1 also use that address space. evalbd.book : ch3 page 18 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-19 1.0 register dump utility this register dump utility has been provided for use on the lansc310 microcontroller evaluation board. it is intended to provide an easy-to-use register- manipulation program. this program displays the index registers in the lansc310 microcontroller, grouped by functionality: ? lansc310 pmu registers screen 1 ? lansc310 pmu registers screen 2 ? lansc310 mmu/isa registers these registers can be read or written by simply entering a new value and pressing return. some registers do not allow full read/write access. read-only registers display the contents of the register but do not allow the user to write a new value. write-only registers allow a user to write a new value to the register. when a value is read from the register, it displays meaningless values. the following is a list of commands available in regdump.exe : arrow keys move the cursor from register to register within the screen. s toggles between the register screens. v allows user to enter a new value for the selected register. b switches the display to a bit-by-bit definition of the selected register. m switches the display to an options menu screen. p dumps all four register screens to an ascii text file called regdump.log . qexits from regdump.exe . the register value display is read from the registers each time the screen is toggled. since the display is not updated with each write, it is possible that a register could appear to be written to, but if it is a read-only register it remains unchanged. please refer to the lansc310 microcontroller programmers reference manual to determine if the register being manipulated has any read/write restrictions. note: this regdump utility is used for both the lansc300 and lansc310 microcontrollers. however, some registers or some bits within registers are used only on the lansc300. these registers or bits are marked with an "lansc300 only" indicator on the regdump screens. evalbd.book : ch3 page 19 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 3-20 1.0 evalbd.book : ch3 page 20 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual 4-1 chapter 4 developing code this document is meant to aid the programmer who is developing bios code, power management code, etc. using the lansc310 microcontroller evaluation board. this evaluation board was designed to support a number of different system configurations (e.g., full isa bus mode, application rom support, ide drives, floppy drive, etc.). this document explains how to configure the lansc310 microcontroller on the evaluation board in order to support these configurations. see the following sections for more information: ? programmable general purpose (pgp) pins on page 4-2 ? power management control (pmc) pins on page 4-3 ? programming bios flash/eprom or application flash/eprom on page 4- 5 ? evaluation boards memory map on page 4-7 ? evaluation boards i/o map on page 4-10 ? evaluation boards irq mapping on page 4-11 ? evaluation boards dma mapping on page 4-13 ? evaluation boards components on page 4-14 ? enabling the lansc310 internal serial port on page 4-15 for more information on the lansc310 microcontroller, see the lansc310 microcontroller data sheet and the lansc310 microcontroller programmers reference manual . evalbd.book : ch4 page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-2 1.0 programmable general purpose (pgp) pins the lansc310 microcontroller has four programmable general purpose (pgp) pins which can be set up as inputs, outputs, address decodes, and address decodes that are gated with the i/o read or i/o write pulse. index registers for the pgp pins are write only. keep this in mind when writing to index 91h, which controls all pgp pins. remember, this particular implementation of the pgp pins is specific to the lansc310 microcontroller evaluation board only . other system designs may implement these pins differently. the lansc310 microcontroller evaluation board makes use of the pgp pins as follows. pgp0 this pin in used to clock data from the data bus into a flip-flop that is used to control the programming voltage to the rom sockets. pgp0 must be set up to gate with the i/o write command. this is done by setting the lansc310 index 91h to xxxxxx10b. index 89h is used to set up the i/o address for pgp0. setting index 89h to a 20h programs pgp0 to respond to writes to i/o addresses 100hC107h. pgp0 must also be enabled as an output. this is done by writing bit 6 of the lansc310 index 70h to a 1. by programming this pin as just described, the lansc310 microcontroller is now able to write to the 1 bit register at i/o port 100h. when set up as described, the write-only register at i/o address 100 is as shown in the table below. note: this pin is referenced as pgpa on the evaluation board schematics beginning in schematics on page d-1. table 4-1. i/o address 100C107 bit description 7C3 reserved 21 = v pp line to rom sockets set to 12 v 0 = v pp line to rom sockets set to 5 v 1not used 0not used evalbd.book : ch4 page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-3 1.0 pgp1 this pin is used as an address decode for the ide cs0 . it should be programmed as an address decode for i/o addresses 1f0hC1f7h. setting the lansc310 microcontrollers index 91h to xxxx11xxb programs pgp1 as an address decode. setting lansc310 index 9ch to 3eh sets the address range to 1f0hC1f7h. pgp1 must also be enabled as an output for the evaluation board. this is done by setting bit 2 of the lansc310 index 74h. note: this pin is referenced as pgpb on the evaluation board schematics beginning in schematics on page d-1. pgp2 this pin is used as an address decode for the ide cs1 . it should be programmed as an address decode for i/o addresses 3f0hC3f7h. setting the lansc310 index 91h to xx11xxxxb programs pgp2 as an address decode. setting the lansc310 index 94h to 7eh sets the address range to 3f0hC3f7h. note: this pin is referenced as pgpc on the evaluation board schematics beginning in schematics on page d-1. pgp3 this pin has no specific function on the lansc310 microcontroller evaluation board. note: this pin is referenced as pgpd on the evaluation board schematics beginning in schematics on page d-1. power management control (pmc) pins the lansc310 microcontroller has five power management control (pmc) pins that can be programmed high or low based on the current power management mode. the lansc310 microcontroller evaluation board makes use of the pmc pins as follows. evalbd.book : ch4 page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-4 1.0 pmc0 this pin is logically ored with the system reset pin from the lansc310 microcontroller (rstdrv) and fed to the reset pin of the 8042 keyboard controller. it is used to perform a software reset to the 8042. a value of 1 drives the reset pin of the 8042 active. a value of 0 allows for normal operation. the lansc310 microcontroller index ach bits 3:0 control pmc0 and are set to 0 on power-up. if you are not using pmu states that turn off the low speed pll (i.e., doze, sleep or suspend modes) then you do not need to change the settings for this pin. refer to 8042 keyboard controller on page 4-14 for a further explanation of when you need to do a software reset. pmc1 this pin is not used on this board. pmc2 this pin is used to select whether the internal lansc310 microcontroller (serial port 1) and the super i/o (serial port 2) are enabled for rs232 serial data (pmc2=1), or whether the ir transmitter/receiver pair is used to send and receive serial data on serial port 1, and serial port 2 transmission is disabled (pmc2=0). the lansc310 indexes 80h and 81h control the state of pmc2. pmc3 this pin is not used on this board. pmc4 this pin is used to mask the system reset pin from the 8042 keyboard controller that is fed to the reset cpu pin (rc ) of the lansc310 microcontroller. a value of 1 holds the cpus rc input high, and prevents the 8042 keyboard controllers reset output from reaching the cpu. a value of 0 allows for normal operation. the lansc310 index ach bits 3:0 control this pin and are set to 0 on power-up. if you are not using pmu states doze, sleep, suspend or off, then you do not need to change the settings for this pin. evalbd.book : ch4 page 4 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-5 1.0 programming bios flash/eprom or application flash/eprom this section describes how to program a flash or eprom device located in the bios sockets (u20 or u59), and the application sockets (u16, u17, u18, u19). the following items need to be addressed: ? controlling the programming voltage for 12-v parts such as the amd 28f020a ? enabling writes to the bios and application rom sockets ? address mapping of the flash sockets ? evaluation board jumper settings controlling v pp there is one control for the v pp line for all bios and application rom sockets (i.e., there is no way to individually control the v pp line for each socket). as described in the section programmable general purpose (pgp) pins on page 4-2, pgp0 is used to clock the flip flop that controls the programming voltage to the rom sockets. when data bit 2 is set to 1, v pp is set to 12 v for all rom sockets. see initialization example for flash programming on page 4-7. enabling writes to the bios and application rom sockets writes to the bios sockets and application sockets need to be specifically enabled (they are disabled by default). this is accomplished by setting to a 1 bits 6 and 5 of the lansc310 index 62h. note: accesses to the bios socket or application socket are isa cycles plus the additional romcs or doscs signal going active. no special logic has been added to the evaluation board to stop a romcs or doscs cycle from going to the isa bus. because of this, if the lansc310 microcontroller is in full isa mode, an isa card (such as a vga card) set up to respond to a memory range interferes with cycles going to the application or bios sockets. for example, a vga card with on-board bios responds to the address range from a0000h through c7fffh. an access to the application rom socket through the mms page to an offset in this range causes both the vga card and the application rom to respond. the only way to avoid this is by either not accessing this range, or reworking the evaluation board. evalbd.book : ch4 page 5 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-6 1.0 address mapping of the flash/eprom sockets the bios sockets have an 8-bit interface. only one socket (u20) or (u59) can be enabled depending on the setting of jumper jp32. address lines a0Ca17, 256k addressing, are connected to the socket. the bios rom can be accessed for programming by either using an mms page, or setting up a linear decode region (see the lansc310 microcontroller programmers reference manual ). typically, an mms page is used. the application sockets have a 16-bit interface. if bios does not already enable the 16-bit interface, this needs to be done after boot-up by setting to a 1 bit 1 of the lansc310 index 51h. even addresses access sockets u16 and u18. odd addresses access sockets u17 and u19. support for both 256kx8 flash or eprom, and 512kx8 eprom parts exists. jumper jp13 controls which is selected. note: 512kx8 flash can be supported after a minor board rework. contact your local amd or distributor field application engineer for more information. when set for 256kx8 parts: even addresses from 0C7fffeh access socket u16; odd addresses from 1C7ffffh access socket u17; even addresses from 80000hC ffffeh access socket u18; and odd addresses from 80001hCfffffh access socket u19. when set for 512kx8 parts: even addresses from 0Cffffeh access socket u16; odd addresses from 1Cfffffh access socket u17; even addresses from 100000hC 1ffffeh access socket u18; and odd addresses from 100001hC1fffffh access socket u19. the application address space is accessed by using an mms page or by enabling the linear decode for the application rom. using an mms page is recommended because it can be accessed using real mode addressing. evaluation board jumper settings there are three jumpers which affect flash programming on the lansc310 microcontroller evaluation board. jp32: this jumper controls whether bios socket u20 (jp32=2-3) or socket u59 (jp32=1-2) is used. jp12: this jumper must be set to 1-2 when flash parts are used (jp12=2-3 indicates eprom parts). evalbd.book : ch4 page 6 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-7 1.0 jp13: this jumper must be set to 1-2 to indicate 256kx8 parts are in the application sockets. (jp13=2-3 indicates 512kx8 parts, and 512kx8 flash is only supported after a minor board rework. contact your local amd or distributor field application engineer for details.) initialization example for flash programming 1. set up pgp0 for i/o address 100h: elan index 91h = 3eh ;sets up pgp0 to be gated with i/o write, keep settings for pgp1 and 2 elan index 89h = 20h ;set up pgp0 to respond to addresses 100-107. elan index 70h = 40h; ;set up pgp0 as an output. do a read, modify, write, setting bit 6. 2. enable writes to bios and application rom: elan index 62h = 70 ;set bits 6,5 = 1. note: bit 4 = 1 assuming 33mhz operation. 3. enable 16-bit interface to application rom: elan index 51h = 02h ;bit 1 =1, indicates 16-bit application rom size. evaluation boards memory map because the lansc310 microcontroller and the evaluation board are so configurable, there is not one single memory map that covers all cases. what is illustrated here is a typical memory map for the evaluation board configured in full isa mode with a trident vga isa card, rom-dos kernel, and 2 mbyte dram. evalbd.book : ch4 page 7 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-8 1.0 table 4-2. typical full isa memory map note: 1. in the above configuration, mmsb is disabled, and mmsa is defined to start at base address c0000h (i.e., lansc310 index 6dh=00). 2. mmsa pages 0 and 1 are disabled allowing accesses to the address range at c0000hCc7ffffh to propagate to the isa bus where the vga bios is located. 3. addresses e0000hCfffffh are set up as linear decodes to the bios rom (index 65h, bit 0=0, bit 1=1, bit 2=0, bit 3=0). during bios initialization, if shadowing is enabled (lansc310 index 65h bit 4=1, lansc310 index 69h=ffh), then accesses to this address range go to dram. 4. refer to the lansc310 microcontroller programmers reference manual for information on rom bios and rom dos accesses using the mms pages. 386 physical address memory type accessed special notes 1fffffhC 100000h dram. fffffhC e0000h bios rom (romcs ). 64k bios image + rom-dos kernel. romcs is set up for lin- ear decode. may be shad- owed to dram. dffffhC d0000h unused. cffffhC cc000h application rom (doscs ). used by rom-dos. mmsa page 3. cbfffh C c8000h dram at offset c8000hCcbfffh. used for smm save state area. mmsa page 2. c7fffhC c0000h isa bus. vga card 32k bios rom. mmsa pages 0 & 1. dis- abled to allow accesses to pass through to isa bus. bffffh C a0000h isa bus. vga card display buffers. mmsb is disabled which allows accesses to propa- gate to isa bus. 9ffffh C 00000h dram. evalbd.book : ch4 page 8 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-9 1.0 dos rom/application rom mapping the application rom space (also known as dos rom space) is selected by the doscs chip select. only 256kx8 flash parts are supported; 256kx8 and 512kx8 eproms are supported. jp12 selects between flash/eprom (1-2 = flash, 2-3 = eprom). jp13 selects between 256kx8 and 512kx8 parts (1-2 = 256k, 2-3 = 512k). note: 512kx8 flash can be supported after a minor board rework. contact your local amd or distributor field application engineer for more information. access to the application rom begins at offset 0h, and extends up to 1fffffh, depending on the size and number of parts installed. application rom is accessed through the mms windows. it is also possible to access linear decoded application rom. this requires setting up lansc310 index b8h. however, the processor must be set up to access memory above the 1 mbyte boundary. bios rom mapping bios rom mapping is similar to application rom mapping. bios rom is selected by the bioscs chip select. 128kx8 and 256kx8 flash and eprom devices are supported. access to the bios rom begins at offset 0h, and extends up to 3ffffh, depending on the size of the device. typically the bios rom is accessed through a linear decode set up for the address range e0000h through fffffh. this is set up using lansc310 index register 65h. it is also possible to access the bios rom using pages in the mms windows. evalbd.book : ch4 page 9 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-10 1.0 evaluation boards i/o map because the lansc310 microcontroller and the evaluation board are so configurable, there is not one single i/o map that covers all cases. what is illustrated here is a typical memory map for the evaluation board configured in full isa mode with the lansc310 microcontroller internal serial port enabled as com1, the super i/o floppy drive controller enabled, an ide hard drive, and the super i/o serial port enabled as com2. table 4-3. typical full isa i/o map i/o address device accessed special notes 3f8hC3ffh lansc310 internal 16c450 uart 3f0hC3f7h ide drive cs1, super i/o floppy drive controller ide cs1 selected using pgp2. only addresses 3f6 and 3f7 bit 7 are used for ide accesses. 3b0hC3dfh trident vga card 3bchC3bfh should be excluded from this range. they are used for parallel port accesses. note this is a general ad- dress range. not all i/o locations in this range are used. 3bchC3bfh lansc310 parallel port enabled as lpt1: other i/o ranges for the lansc310 parallel port are 378hC37fh and 278hC 27fh. 398hC399h super i/o index and data ports used to enable super i/o functions. 2f8hC2ffh super i/o serial port enabled as com2 1f0hC1f7h ide drive cs0 ide cs0 selected using pgp1. 10chC10fh reserved 108hC10bh reserved 100hC107h pgp0 decode for v pp control set up using lansc310 index 89h. (refer to programmable general pur- pose (pgp) pins on page 4-2.) echCefh reserved e8hCebh reserved c0hCdeh dma controller channels 4C7 (internal to the lansc310) see 8237a spec. a0h, a1h programmable irq slave controller (internal to the lansc310) see 8259 spec. evalbd.book : ch4 page 10 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-11 1.0 note: all i/o addresses are at at-compatible locations. evaluation boards irq mapping because the lansc310 microcontroller and the evaluation board are so configurable, there is not one single irq map that covers all cases. what is illustrated here is a typical memory map for the evaluation board configured in full isa mode with the lansc310 microcontroller internal serial port enabled as com1, the super i/o floppy drive controller enabled, an ide hard drive, and the super i/o serial port enabled as com2. 92h lansc310 internal gate a20 and reset control (internal to the lansc310) refer to the lansc310 microcontrol- ler programmers reference manual . 80hC8fh dma page registers. channels 0C7 (internal to the lansc310). 70hC71h rtc index and data registers (internal to the lansc310). nmi enable/disable (bit 7 of port 70). mmsb is disabled which allows ac- cesses to propagate to isa bus. 60h, 64h 8042 keyboard control and data regis- ter see 8042 spec. 61h port b control (internal to the lansc310) 40hC43h programmable timer registers (internal to the lansc310) see 8254 spec. 20h, 21h programmable irq master controller (internal to lansc310) see 8259 spec. 0hCfh dma controller channels 0C3 (inter- nal to the lansc310) see 8237a spec. i/o address device accessed special notes evalbd.book : ch4 page 11 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-12 1.0 table 4-4. typical full isa irq mapping note: 1. irq lines 3, 4, 5, 6, 7, 9, 10, 11, 12, 14 and 15 are available on the isa bus. care must be taken so that cards on the isa bus do not use interrupts that conflict with internal lansc310 devices or each other. irq device assigned special notes 15 available for isa bus 14 connected to ide interface 13 reserved 12 available for isa bus 11 available for isa bus 10 available for isa bus 9 available for isa bus 8 lansc310 internal rtc interrupt 7 lansc310 internal parallel port 6 super i/o floppy drive controller 5 available for isa bus 4 internal serial port; com1 3 connected to super i/o for com2 connects to irq3 pin on super i/o 2 used to cascade to slave pic (8259) 1 keyboard buffer full (driven by 8042) 0 timer 0 output (internal to lansc310) typically used for dos clock evalbd.book : ch4 page 12 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-13 1.0 evaluation boards dma mapping the following table is the dma mapping for the lansc310 microcontroller evaluation board. table 4-5. typical full isa dma mapping dma device assigned special notes 7 isa bus 16-bit i/o accesses 6 isa bus 16-bit i/o accesses 5 isa bus 16-bit i/o accesses 4 reserved used to cascade dma channels 0C3 3 isa bus 8-bit i/o accesses 2 super i/o floppy drive controller 8-bit i/o accesses 1 isa bus also used for memory-to-memory transfers with dma channel 0 0 isa bus also used for memory-to-memory transfers with dma channel 1 evalbd.book : ch4 page 13 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-14 1.0 evaluation boards components 8042 keyboard controller the evaluation board uses a non-static 8042 keyboard controller. what this means to the programmer is that if sysclk stops being driven to the 8042 for any period of time, the controller must be reset once sysclk starts being driven again in order for the 8042 to function properly. the lansc310 microcontroller stops driving sysclk any time the low speed pll is disabled or when in sleep, suspend and off pmu modes even if the low speed pll is enabled for these modes. one side effect of not driving sysclk to the 8042 is the rc pin from the 8042 will go active for a short period of time. this active state is latched by the lansc310 microcontroller. therefore when the lansc310 microcontroller goes back to high speed pll mode from sleep, suspend or off mode, the cpu is reset. note that the above conditions only apply to a non-static 8042. if a static 8042 is used, then these conditions dont apply. to work around these situations, the evaluation board has been wired to use two pins on the lansc310 microcontroller to gate rc from the 8042 (pmc4) and to reset the 8042 (pmc0). pmc4 should be programmed to mask off the rc pin from the 8042 while in sleep, suspend, and off modes to prevent the cpu from being reset due to sysclk not being driven out of the lansc310. (if the low speed pll is to be disabled in doze mode then pmc4 should be driven for this mode as well.) when the system goes back to high speed pll mode, the 8042 needs to be reset by pulsing pmc0 high for 1 millisecond. commands should also be issued to the 8042 to re-enable the keyboard. see pmc0 on page 4-4 and pmc4 on page 4-4 for more information. national super i/o pc87322vf the super i/o is set up to decode address 398h and 399h for its index and data registers. when configuring the serial port on the super i/o it is important to note that irq3 from the chip is connected to pirq0 on the lansc310 microcontroller. (note: pirq0 on the lansc310 is internally set to irq3 when in full isa bus mode; it is programmable in all other bus modes.) irq4 from the super i/o is not connected. therefore when configuring the serial port in the super i/o, only configure it to use irq3. also pmc2 must be set to 1 in order to enable the rs232 drivers for the serial port. evalbd.book : ch4 page 14 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-15 1.0 the super i/o parallel port is not connected and therefore should not be enabled. the floppy drive interface on the super i/o is enabled. dma channel 2 is used and the floppy irq is connected to pirq1 on the lansc310 microcontroller. (note: pirq1 on the lansc310 is internally set to irq6 when in full isa bus mode; it is programmable in all other bus modes.) ide interface an ide drive can be directly connected to the lansc310 microcontroller. on the evaluation board, data bit 7 is routed through the super i/o in order to properly handle bit 7 for i/o addresses 3f6 and 3f7, which are jointly used by the floppy and the ide interface. the irq line from the ide connector is connected to irq14 on the lansc310 microcontroller. pgp1 is used for the ide chip select 1 (i/o address 1f0C1f7h). pgp2 is used for ide chip select 2 (i/o address 3f6C3f7). see connecting an ide hard drive on page 1-7 for the steps to connect the drive. enabling the lansc310 internal serial port the lansc310 microcontroller internal serial port is typically configured as com1. the following lansc310 index registers need to be set for this configuration: ? elan index 77h = 90h ; enable internal uart to base address 3f8 and irq 4 (com1) ? elan index 92h = 01h ; enable clock to uart ? elan index 48h = 02h ; set for 16c450 compatibility ? set pin pmc2 active for all pmu modes (refer to power management control (pmc) pins on page 4-3). the uarts i/o registers 3f8hC3ffh can now be accessed to perform serial transfers. evalbd.book : ch4 page 15 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual 4-16 1.0 evalbd.book : ch4 page 16 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual a-1 appendix a evaluation board setup summary this appendix summarizes the jumper and switch settings of the lansc310 microcontroller evaluation board. for the location of these parts on the board, see figure 2-1 on page 2-2. evalbd.book : appa page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual a-2 1.0 table a-1. bus mode selection and affected jumpers table a-2. configuration jumpers 1C 512kx8 flash can only be supported after a minor board rework. contact your local amd or distributor field application engineer for more information 2C cannot be set in full isa or local bus mode. bus mode resistor pack setting jp16 jp17 jp18 1-2 2-3 1-2 2-3 open closed full isa install rp1 & rp2 only n/a n/a connects irq3 from super i/o n/a n/a connects irq12 from mouse local bus install rp5 & rp6 only 2x cpu clock n/a connects irq3 from super i/o n/a n/a connects irq12 from mouse 3 position jumpers system affected 1-2 2-3 jp12 dos rom & bios selects flash selects eprom device jp13 dos sockets 256kx8 512kx8 1 jp16 local bus mode cpu clock 2x n/a jp17 super i/o serial port ps/2 mouse enables super i/o serial port irq n/a 2 jp18 (see table a-3 on page a-3) jp32 bios rom socket u59 (phoenix) u20 (systemsoft) evalbd.book : appa page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual a-3 1.0 table a-3. jp18 table a-4. switches mode pin setting function isa or local bus closed enables ps/2 port (connects irq12 from 8042 to irq12 on lansc310 device) sw3: on off 1 nc nc 2 connects vgardy to vlrdyi open 3 connects vlrdyo to vlrdyi open 4 nc nc sw4: on off 1 memory = 5 v memory = 3.3 v 2 connects pirq1 to lansc310 device disconnects pirq1 from lansc310 device 3 connects irq1 to lansc310 device disconnects irq1 from lansc310 device 4 bl1 = gnd bl1 = 5v 5 bl2 = gnd bl2 = 5v 6 bl3 = gnd bl3 = 5v 7 bl4 = gnd bl4 = 5v 8 acin = gnd acin = 5v evalbd.book : appa page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual a-4 1.0 table a-5. power measurement jumpers note: be sure to turn off system power before removing jp1Cjp11. replace jp1C11 before power-up or the system will not work. jumper v cc logic connected to v cc plane jp1 v cc lansc310 core v cc only. always 3.3 v. jp2 v cc3 lansc310 av cc pin. analog v cc . always 3.3 v. jp3 v cc5 lansc310 v cc5 pin. diode clamp refs except v cc mem and av cc source pins. always 5 v except in full 3.3- v designs. (evaluation board limits to 5 v.) jp4 v ccmem lansc310 memory interface v cc . see the sw4 table on page 2-19 for 3.3-v or 5-v setting. restrictions do apply. also the diode clamp ref for pins sourced to the v ccmem pin. jp5 v ccsys lansc310 isa bus v cc and other misc. pins. 5 v or 3.3 v. refer to datasheet for details. jp6 v ccsys2 lansc310 alternate pin v cc . 5 v or 3.3 v. refer to datasheet for details. jp7 v ccmem53 system dram v cc plane. jp10 v cckbos 8042 v cc jp11 v ccrom bios and application rom v cc jp19 v cc1 lansc310 v cc1 pin 176. 5 v or 3.3 v. evalbd.book : appa page 4 thursday, august 8, 1996 2:34 pm
1.0 lansc310 microcontroller evaluation board users manual b-1 appendix b verified peripherals this a list of peripherals that have been verified to work on the lansc310 microcontroller evaluation board: *C note that connor and fujitsu hard drives do not work with this board. peripheral manufacturer model # floppy drive mitsumi d359t3 teac fd-235hf hard drive* quantum prodrive lps series western digital caviar series power supply dtk computer inc. pip-151 transworld tw-1800r jabert we-d250 keyboard keytronic kt2000 series mitsumi kpq-e99yc vga monitor ctx 6439 nec multisync 5fge video card aved av540 trident tvga 9000i evalbd.book : appb page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual b-2 1.0 evalbd.book : appb page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual c-1 1.0 appendix c board layout suggestions the following suggestions concern the lansc310 microcontroller evaluation board layout strategy for the 32-khz oscillator, the plls, and the power supplies. the goal is to minimize noise and noise coupling associated with the way the board is laid out. special care is needed to minimize board leakages which can be fatal to pins that are sensitive to leakage currents, such as the two crystal oscillator pins, xtal1 and xtal2. 32-khz oscillator prudent board layout for the 32-khz oscillator suggests the following precautions: ? keep the two traces, xtal1 and xtal2, as short as possible, especially the input trace, xtal1. xtal1 is extremely sensitive to leakage. total leakage from/to xtal1 to/from all the pins on the board must be kept under 300 na. xtal2 can tolerate a leakage as high as 900 na. ? keep all noisy signals (e.g., pll outputs and other clocking signals) as far away from xtal1 and xtal2 as possible. again, xtal1 is much more sensitive to noise coupling than xtal2. ? minimize parasitic capacitance between xtal1 and xtal2; even a few picofarads can potentially cause the oscillation frequency to be off target. ? do not use a feedback resistor larger than 20 m w ; it may fail to start up if the leakage at xtal1 is equivalent to 5m w or less. the feedback resistor value can be lowered to counter leakage at xtal1, but that increases start-up time. the lower bound for the feedback resistor should be about 10 m w . ? the capacitors connected between xtal1, xtal2, and analog ground should be between 15 pf and 30 pf, and they should be about equal in value. increasing the two capacitor values increases start-up time and power consumption, but it does reduce noise coupling into xtal1 and xtal2. evalbd.book : appc page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual c-2 1.0 phase-locked loops board layout considerations for the four plls suggest the following precautions: ? keep the output traces for the four plls as short as possible and keep them as far away from each other (and other clocking signals) as possible. ? do not exceed the specified ac loading for the four pll outputs. certainly no dc loading is allowed since they are all cmos logic outputs. if the plls have to drive more load than they are designed for in the actual application, make sure they are properly buffered on the board. power supplies board layout considerations for the power supplies suggest the following precautions: ? bring the analog v cc and digital v cc on separate traces from the output of the voltage regulator to the lansc310 microcontroller; making sure the traces are thick and wide. filter the analog v cc with an rlc second-order low-pass filter (e.g., r= 10 w , l=47 m h, c=33 m f). since the digital v cc carries much more current than the analog v cc , a second order lc low-pass filter should be used instead (i.e., the series resistor should be removed). a small capacitor in the order of a few nanofarads can be added in parallel to the large filter capacitor to suppress high-frequency noise. ? isolate the analog ground plane from the digital ground plane on the board, and connect them after decoupling. evalbd.book : appc page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual d-1 1.0 appendix d schematics the schematics beginning on page d-2 are the actual orcad schematics used to build the lansc310 microcontroller evaluation board. these schematics are useful for understanding and modifying the evaluation board. since the evaluation board incorporates many different possible configurations for the lansc310 microcontroller, these schematics are not a good place to start for actual lansc310 microcontroller-based designs. evalbd.book : appd page 1 thursday, august 8, 1996 2:34 pm
date: march 29, 1996 sheet 1 of 23 size document number rev b elansc300/310 evaluation board 2.2 title elansc300/310 208-pin qfp chip amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. |link p 2 p 3 |fsocket.sch p 4 p 5 p 6 p 7 p 8 p 9 p 10 p 11 p 12 p 13 p 14 |header.sch |misc.sch |33opt.sch |dram.sch |sram.sch |bufrom.sch |keybrd.sch |biosdos.sch |pcmbufct.sch |pcmbcon.sch |pcmnbcon.sch |cgavideo.sch smi acin pmc0 pmc1 pmc2 pmc4 pgpa lph# jtagen resin# pmc3 lf2 lf3 resume# 'sus#/res#' vccel5 vccelsys vccelmem vccelsy2 vccsy253 1 2 jp6 header 2 'x1out[baud_out]' 'ioreset#' vccmem53 1 2 jp4 header 2 1 2 jp5 header 2 vcc5 vccel1 32kout spker lf1 lf4 1 2 jp3 header 2 32kinr vcc1 1 2 jp19 header 2 xioreset# 14mout vccel1 pclk pirq0 dack2# elpclk ovcc3 l3 47uh 1 2 jp2 header 2 gnd r379 10 c229 33uf tant eirq1 epirq1 r1 33 vccsys5 elpclk 'sysclk[xtclk]' 'dack2#[tck]' vccel3 vccel5 vccelsys vccelmem vccelsy2 vccela sysclk 45 sa0 74 sa1 73 sa2 72 sa3 71 sa4 70 sa5 69 sa6 67 sa7 66 sa8 64 sa9 63 sa10 62 sa11 61 sa12 60 d0 42 d1 41 d2 40 d3 39 d4 38 d5 37 d6 36 d7 34 d8 32 d9 31 d10 30 d11 29 d12 28 d13 27 d14 26 d15 25 m a 0 / s a 1 4 2 4 m a 1 / s a 1 5 2 1 m a 2 / s a 1 6 1 9 m a 3 / s a 1 7 1 8 m a 4 / s a 1 8 1 7 m a 5 / s a 1 9 1 6 m a 6 / s a 2 0 1 5 m a 7 / s a 2 1 1 4 m a 8 / s a 2 2 1 3 m a 9 / s a 2 3 1 1 m a 1 0 / s a 1 3 1 0 cas1h#(srcs1#) 5 cas1l#(srcs0#) 4 cas0h#(srcs3#) 7 cas0l#(srcs2#) 6 mwe# 8 ras1# 3 ras0# 2 irq1 195 pirq0(irq3) 194 pirq1(irq6) 193 dack2#(tclk) 46 drq2(tdo) 76 aen(td) 47 tc(tms) 49 sdwrth 51 sdwrtl 50 ior# 54 iow# 55 memr# 56 memw# 57 dbufoe# 59 rstdrv 58 iochrdy 192 a c i n 1 0 1 e x t s m i # 1 0 2 r e s u m e # 1 0 3 p m c 0 1 3 7 p m c 1 1 3 8 p m c 2 7 7 p m c 3 1 8 5 p g p 0 1 8 9 p g p 1 1 8 8 p g p 2 1 8 7 p g p 3 1 8 6 bl1# 106 bl2# 107 bl3# 108 bl4# 109 l p h # 1 9 0 g n d 1 g n d 1 0 4 g n d 1 5 7 g n d 1 0 5 g n d 1 2 1 g n d 1 9 1 g n d 1 5 6 g n d 2 0 g n d 3 3 g n d 5 3 g n d 6 8 sbhe(lcddl1) 143 iocs16#(lcddl0) 196 mcs16#(lcddl1) 197 irq14(lcddl1) 198 l v d d # ( b a l e ) 1 4 5 l v e e # ( i r q 1 5 ) 1 8 2 f r m / v d r v ( i r q 1 2 ) 1 8 1 c p 1 / h d r v ( p r e q / i 1 7 8 c p 2 / v d o ( b u s y # / i 1 7 9 m ( i r q 4 ) 1 7 3 l c d d 0 / i ( d r q 1 ) 1 7 4 l c d d 1 / r ( d a c k 5 # ) 1 4 4 l c d d 2 / g ( d r q 5 ) 1 7 5 l c d d 3 / b ( i o c h c h k 1 7 7 d s c e # ( d a c k 1 # ) 1 4 6 d s o e # ( c p u r d y # / l 1 4 7 d s w e # ( p u l l u p ) 1 8 3 d s m a 0 1 6 5 d s m a 1 ( n a # / i r q 7 ) 1 6 4 d s m a 2 ( c p u r s t ) 1 6 3 d s m a 3 ( c p u c l k ) 1 6 2 d s m a 4 ( a 1 3 / d a c k 6 1 6 1 d s m a 5 ( a 1 4 / d a c k 7 1 6 0 d s m a 6 ( a 1 5 / d a c k 3 1 5 9 d s m a 7 ( a 1 6 / d a c k 0 1 5 8 d s m a 8 ( a 1 7 / l a 1 7 ) 1 5 5 d s m a 9 ( a 1 8 / l a 1 8 ) 1 5 4 d s m a 1 0 ( a 1 9 / l a 1 9 1 5 3 d s m a 1 1 ( a 2 0 / l a 2 0 1 5 2 d s m a 1 2 ( a 2 1 / l a 2 1 1 5 1 d s m a 1 3 ( a 2 2 / l a 2 2 1 5 0 d s m a 1 4 ( a 2 3 / l a 2 3 1 4 9 d s m d 0 ( l d e v # / r e f 1 4 8 d s m d 1 ( l r d y # / d r q 1 6 6 d s m d 2 ( b l e # / i r q 1 1 6 7 d s m d 3 ( b h e # / i r q 9 1 6 8 d s m d 4 ( w _ r # / d r q 7 1 6 9 d s m d 5 ( m _ i o / d r q 3 1 7 0 d s m d 6 ( d _ c # / d r q 0 1 7 1 d s m d 7 ( a d s # / 0 w s # 1 7 2 doscs# 43 romcs# 44 a 2 0 g a t e 7 9 r c # 7 8 8 0 4 2 c s # 7 5 rin# 100 sin 99 dcd# 98 dsr# 97 cts# 96 sout 94 rts# 93 dtr# 92 ppoen# 91 ppdwe#(ppdcs#) 90 init# 89 ack# 88 slctin# 84 error# 86 busy 85 slct 87 strb# 83 pe 82 afdt# 80 ca25 136 ca24 134 bvd2-b 119 bvd1-b 120 wp-b 118 rdy-b# 117 cd-b# 116 rst-b 127 reg-b# 126 vpp-b 125 mcel-b# 123 mceh-b# 124 icdir 122 wait-ab# 115 bvd2-a 113 bvd1-a 114 wp-a 112 rdy-a# 111 cd-a# 110 rst-a 133 reg-a# 132 vpp-a 131 mcel-a# 129 mceh-a# 130 g n d 2 0 8 g n d 5 2 v c c s y s 4 8 v c c s y s 6 5 v c c 2 3 v c c m e m 9 v c c m e m 2 2 v c c m e m 3 5 v c c 8 1 v c c s y s 2 1 4 2 v c c 5 9 5 v c c 1 3 5 v c c 1 1 7 6 v c c 5 1 2 8 v c c 1 8 0 a v c c 2 0 3 s p k r 1 3 9 x i o r e s e t # 1 4 0 l f 4 2 0 7 1 4 m o u t ( b a u d o u t ) 2 0 0 x 3 2 i n 2 0 1 x 3 2 o u t 2 0 2 l f 1 2 0 4 l f 2 2 0 5 l f 3 2 0 6 r e s i n # 1 4 1 j t a g e n 1 9 9 g n d 1 2 p m c 4 1 8 4 u1 elan '8042cs#[xtdat]' vpp1 a20gate pgpd pgpc pgpb 1icrst 8042cs# rc# mce1# mce12# reg1# 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' gnd vccela p 15 p 16 p 17 p 18 p 19 p 20 p 21 p 22 p 23 |serpar.sch |isabus.sch |vlbus.sch |power.sch |upower.sch |powersw.sch |flopide.sch |spares.sch |spares1.sch c11 0.01uf tant vccel3 vccel5 gnd gnd gnd c3 0.1uf c4 0.1uf gnd c189 10uf/10v c1 0.01uf tant wp2 vpp2 bvd12 bvd11 wp1 2icrst icdir cd1# rdy1# wait# mce2# mce22# reg2# cd2# rdy2# 'pullup' 'pullup' 'pullup' 'pullup' 'pullup' 'pullup' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'pullup' 'pullup' 'pullup' sa0 sa1 sa2 sa3 sa4 sa[0..12] d[0..15] 'drq2[tdo]' 'aen[tdi]' 'tc[tms]' sa[0..12] drq2 iochrdy tc aen d[0..15] ior# iow# ememr# ememw# ovcc3 1 2 jp1 header 2 gnd eresdrv c230 33uf tant l4 1.2uh resin# xioreset# 1 2 jp29 *header 2 d0 d1 d2 d3 d4 d5 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 208-pqfp elansc300/310 pe busy slct bvd22 bvd21 isa24 isa25 ack# init# err# afdt# strb# slctin# ppdwe# '[ppdsc#]' '[x14out]' 'rsvd' 'rsvd' 'pullup' 'pullup' vccelsys vccelmem gnd gnd gnd gnd c5 0.1uf c6 0.1uf c7 0.1uf c8 0.1uf gnd c190 10uf/10v gnd c191 10uf/10v mwe# vccelsy2 gnd c10 0.1uf gnd c186 10uf/10v sin sout dtr# rts# cts# dsr# dcd# ri# ppoen# romcs# doscs# 'rts#/cfg0' 'dtr#/cfg1' schematics provided as is amd makes no warranty expressed or implied. for reference only d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 'dbufoe#' 'endirh' 'endirl' sden# sdrdh sdrdl sden# sdrdh sdrdl remove jp29 if using elansc300 rev b or ELANSC310 without upower mode. install jp29 if using elansc300 rev b or ELANSC310 with upower mode. iocs16# mcs16# irq14 bl1# bl2# bl3# bl4# r9 10k sbhe# r6 1k r7 1k r8 1k vcc1 r2 33 r3 33 r4 33 r5 33 elcs0l# elcs0h# elcs1l# elcs1h# ras0# ras1# cas0l# cas0h# cas1l# cas1h# elcs0h# elcs0l# elcs1h# elcs1l# gnd gnd gnd vccel1 c201 10uf/10v c202 0.1uf c203 0.1uf sa[13..23] sa[13..23] elansc300 chip/schematic signal name note: sa13 sa14 sa15 sa16 sa17 sa18 sa19 sa20 sa21 sa22 sa23 ' b l e # ( i r q 1 1 ) ' ' b h e # ( i r q 9 ) ' ' w - r # ( d r q 7 ) ' ' m - i o # ( d r q 3 ) ' ' d - c # ( d r q 0 ) ' ' a d s # ( o w s # ) ' ' r s v d ( p u l l u p ) ' ' p u l l u p ( i r q 7 ) ' ' c p u r s t ( r s v d ) ' ' c p u c l k ( p u l l u p ) ' ' a 1 3 ( d a c k 6 # ) ' ' a 1 4 ( d a c k 7 # ) ' ' a 1 5 ( d a c k 3 # ) ' ' a 1 6 ( d a c k 0 # ) ' ' a 1 7 ( l a 1 7 ) ' ' a 1 8 ( l a 1 8 ) ' ' a 1 9 ( l a 1 9 ) ' ' a 2 0 ( l a 2 0 ) ' ' a 2 1 ( l a 2 1 ) ' ' a 2 2 ( l a 2 2 ) ' ' a 2 3 ( l a 2 3 ) ' ' l d e v # ( r s v d ) ' ' l r d y # ( d r q 6 ) ' gnd 'a12(bale)' 'irq15' 'irq12' 'pulldn(irq5)' iochrdy frm1 cp11 lvee# lvdd# cp21 dsma[0..14] dsmd[0..7] ld0 ld1 ld2 ld3 m1 dswe# dsce# dsoe# 'pullup(irq10)' 'irq4' 'drq1' 'dack5#' 'drq5' 'iochchk#' 'dack1#' 'cpurdy#(lmeg#)' 'pullup' dsmd[0..7] dsma[0..14] d s m a 0 d s m a 1 d s m a 2 d s m a 3 d s m a 4 d s m a 5 d s m a 6 d s m a 7 d s m a 8 d s m a 9 d s m a 1 0 d s m a 1 1 d s m a 1 2 d s m a 1 3 d s m a 1 4 d s m d 0 d s m d 1 d s m d 2 d s m d 3 d s m d 4 d s m d 5 d s m d 6 d s m d 7 'ELANSC310 chip signal name'
date: march 29, 1996 sheet 2 of 23 size document number rev b elansc300/310 evaluation board 2.2 title elansc300 socket - 208 pin pga socket amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. smi acin pmc0 pmc1 pmc2 pmc4 pgpa lph# jtagen resin# pmc3 resume# slf2 slf3 spker slf1 slf4 xioreset# 14mout p32kout p32kinr vccel1 gnd r380 10 ovcc3 vccpela c231 33uf tant eirq1 epirq1 l5 47uh pirq0 dack2# elpclk vccel5 vccelsys vccelmem vccelsy2 elpclk sysclk r1 sa0 t7 sa1 u7 sa2 r7 sa3 u6 sa4 t6 sa5 p9 sa6 u5 sa7 p7 sa8 r6 sa9 u3 sa10 p8 sa11 t4 sa12 r5 d0 m3 d1 p1 d2 n2 d3 n1 d4 m2 d5 m1 d6 l3 d7 l2 d8 k3 d9 k1 d10 k2 d11 j1 d12 j3 d13 j2 d14 h2 d15 k4 m a 0 / s a 1 4 h 3 m a 1 / s a 1 5 g 1 m a 2 / s a 1 6 f 1 m a 3 / s a 1 7 f 2 m a 4 / s a 1 8 j 4 m a 5 / s a 1 9 e 2 m a 6 / s a 2 0 e 1 m a 7 / s a 2 1 g 4 m a 8 / s a 2 2 d 1 m a 9 / s a 2 3 c 1 m a 1 0 / s a 1 3 h 4 cas1h#(srcs1#) c2 cas1l#(srcs0#) d3 cas0h#(srcs3#) b1 cas0l#(srcs2#) e4 mwe# e3 ras1# a1 ras0# f4 irq1 a5 pirq0(irq3) c7 pirq1(irq6) a6 dack2#(tclk) n3 drq2(tdo) r8 aen(td) r2 tc(tms) t1 sdwrth r3 sdwrtl n4 ior# p6 iow# u1 memr# p4 memw# t3 dbufoe# u2 rstdrv r4 iochrdy b7 a c i n u 1 6 e x t s m i # r 1 4 r e s u m e # r 1 5 p m c 0 g 1 7 p m c 1 g 1 6 p m c 2 t 9 p m c 3 a 9 p g p 0 a 7 p g p 1 b 8 p g p 2 a 8 p g p 3 b 9 bl1# m14 bl2# u17 bl3# n14 bl4# r16 l p h # c 8 g n d b 2 g n d p 1 4 g n d b 1 6 g n d t 1 6 g n d j 1 4 g n d d 6 g n d d 1 2 g n d g 3 g n d l 1 g n d t 2 g n d t 5 sbhe(lcddl1) e17 iocs16#(lcddl0) b6 mcs16#(lcddl1) a4 irq14(lcddl1) b5 l v d d # ( b a l e ) d 1 7 l v e e # ( i r q 1 5 ) b 1 0 f r m / v d r v ( i r q 1 2 ) d 7 c p 1 / h d r v ( p r e q / i b 1 1 c p 2 / v d o ( b u s y # / i a 1 1 m ( i r q 4 ) d 9 l c d d 0 / i ( d r q 1 ) b 1 2 l c d d 1 / r ( d a c k 5 # ) f 1 6 l c d d 2 / g ( d r q 5 ) a 1 3 l c d d 3 / b ( i o c h c h k a 1 2 d s c e # ( d a c k 1 # ) e 1 6 d s o e # ( c p u r d y # / l d 1 6 d s w e # ( p u l l u p ) a 1 0 d s m a 0 b 1 4 d s m a 1 ( n a # / i r q 7 ) c 1 4 d s m a 2 ( c p u r s t ) a 1 6 d s m a 3 ( c p u c l k ) d 1 4 d s m a 4 ( a 1 3 / d a c k 6 b 1 5 d s m a 5 ( a 1 4 / d a c k 7 d 1 5 d s m a 6 ( a 1 5 / d a c k 3 a 1 7 d s m a 7 ( a 1 6 / d a c k 0 d 8 d s m a 8 ( a 1 7 / l a 1 7 ) c 1 5 d s m a 9 ( a 1 8 / l a 1 8 ) e 1 4 d s m a 1 0 ( a 1 9 / l a 1 9 b 1 7 d s m a 1 1 ( a 2 0 / l a 2 0 e 1 5 d s m a 1 2 ( a 2 1 / l a 2 1 c 1 6 d s m a 1 3 ( a 2 2 / l a 2 2 f 1 5 d s m a 1 4 ( a 2 3 / l a 2 3 c 1 7 d s m d 0 ( l d e v # / r e f d 1 3 d s m d 1 ( l r d y # / d r q d 1 0 d s m d 2 ( b l e # / i r q 1 a 1 5 d s m d 3 ( b h e # / i r q 9 c 1 3 d s m d 4 ( w _ r # / d r q 7 a 1 4 d s m d 5 ( m _ i o / d r q 3 c 1 2 d s m d 6 ( d _ c # / d r q 0 d 1 1 d s m d 7 ( a d s # / 0 w s # b 1 3 doscs# p2 romcs# p5 a 2 0 g a t e p 1 0 r c # t 8 8 0 4 2 c s # u 8 rin# r13 sin t15 dcd# r12 dsr# u15 cts# p13 sout t13 rts# u14 dtr# p11 ppoen# u13 ppdwe#(ppdcs#) t12 init# u12 ack# r11 slctin# r10 error# t11 busy u11 slct p12 strb# u10 pe t10 afdt# r9 ca25 h15 ca24 h16 bvd2-b n17 bvd1-b n16 wp-b l14 rdy-b# p17 cd-b# m15 rst-b k17 reg-b# l16 vpp-b l17 mcel-b# m17 mceh-b# l15 icdir m16 wait-ab# r17 bvd2-a p16 bvd1-a k14 wp-a n15 rdy-a# t17 cd-a# p15 rst-a j17 reg-a# j15 vpp-a h14 mcel-a# j16 mceh-a# k16 g n d d 4 g n d l 4 v c c s y s p 3 v c c s y s u 4 v c c h 1 v c c m e m d 2 v c c m e m g 2 v c c m e m m 4 v c c u 9 v c c s y s 2 g 1 5 v c c 5 t 1 4 v c c h 1 7 v c c 1 c 1 1 v c c 5 k 1 5 v c c c 1 0 a v c c b 3 s p k r f 1 4 x i o r e s e t # g 1 4 l f 4 c 3 1 4 m o u t ( b a u d o u t ) d 5 x 3 2 i n a 3 x 3 2 o u t c 6 l f 1 c 5 l f 2 a 2 l f 3 c 4 r e s i n # f 1 7 j t a g e n b 4 g n d f 3 p m c 4 c 9 u? elanpga vpp1 a20gate pgpd pgpc pgpb 1icrst 8042cs# rc# mce1# mce12# reg1# gnd vccpela c12 0.01uf tant vccel5 gnd gnd gnd c167 0.1uf c168 0.1uf vccpel3 c166 0.01uf tant wp2 vpp2 bvd12 bvd11 wp1 2icrst icdir cd1# rdy1# wait# mce2# mce22# reg2# cd2# rdy2# sa0 sa1 sa2 sa3 sa4 sa[0..12] drq2 iochrdy tc aen d[0..15] iow# ior# sa[0..12] d[0..15] ememw# ememr# eresdrv gnd ovcc3 vccpel3 c232 33uf tant l6 1.2uh d0 d1 d2 d3 d4 d5 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 pga elansc300 pe busy slct bvd22 bvd21 isa24 isa25 ack# init# err# afdt# strb# slctin# ppdwe# vccelsys vccelmem gnd gnd gnd gnd c169 0.1uf c170 0.1uf c171 0.1uf c172 0.1uf vccelsy2 gnd c173 0.1uf gnd gnd c204 0.1uf c205 0.1uf vccel1 sin sout mwe# dtr# rts# cts# dsr# dcd# ri# ppoen# romcs# doscs# sden# sdrdl sdrdh d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 sden# sdrdh sdrdl iocs16# mcs16# irq14 bl1# bl2# bl3# bl4# sbhe# ras0# ras1# elcs0h# elcs0l# elcs1h# elcs1l# sa[13..23] sa[13..23] elansc300 pga socket d s m d 2 d s m d 3 d s m d 4 d s m d 5 d s m d 6 d s m d 7 sa13 sa14 sa15 sa16 sa17 sa18 sa19 sa20 sa21 sa22 sa23 d s m a 0 d s m a 1 d s m a 2 d s m a 3 d s m a 4 d s m a 5 d s m a 6 d s m a 7 d s m a 8 d s m a 9 d s m a 1 0 d s m a 1 1 d s m a 1 2 d s m a 1 3 d s m a 1 4 d s m d 0 d s m d 1 gnd frm1 lvee# lvdd# cp11 cp21 dsma[0..14] dsmd[0..7] ld0 ld1 ld2 ld3 m1 dswe# dsce# dsoe# dsmd[0..7] dsma[0..14] - elansc300 only -
date: march 29, 1996 sheet 3 of 23 size document number rev b elansc300/310 evaluation board 2.2 title debug headers amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p3 10th center 30x2 berg amp 3-102977-0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p1 10th center 30x2 berg amp 3-102977-0 mwe# ras0# cas0l# cas1l# d11 d13 d15 sa15 sa17 sa19 sa21 sa23 gnd ras1# cas0h# cas1h# d10 d12 d14 sa13 sa14 sa16 sa18 sa20 sa22 gnd wp2 vpp2 bvd11 wp1 bvd21 2icrst isa24 mce1# reg1# cd1# mce22# cd2# gnd bl1# bl3# 'pullup' 'pullup' 'pullup' 'pullup' 'pullup' 'pullup' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' vpp1 bvd12 bvd22 bl2# bl4# 1icrst icdir isa25 mce12# rdy1# wait# mce2# reg2# rdy2# 'pullup' 'pullup' 'pullup' 'pullup' 'pullup' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' 'rsvd' gnd pmc1 dsoe# dsma8 dsma10 dsma12 dsma14 gnd lvdd# sbhe# 'a12(bale)' 'cpurdy#(lmeg#)' 'a23(la23)' 'a21(la21)' 'a19(la19)' 'a17(la17)' gnd 'ioreset#' 'dack1#' spker pmc0 ld1 resin# dsce# dsma9 dsma11 dsma13 dsmd0 vcc1 xioreset# 'ldev#(rsvd)' 'a22(la22)' 'a20(la20)' 'a18(la18)' drq2 tc sdrdh romcs# d0 d2 d4 d6 d8 gnd 'drq2[tdo]' 'tc[tms]' 'endirh' 'endirh' aen pclk sdrdl doscs# d1 d3 d5 d7 d9 gnd 'sysclk[xtclk]' 'aen[tdi]' 'endirl' sa[0..12] d[0..15] sa[13..23] gnd ior# sa8 sa10 sa12 sa[0..12] d[0..15] sa[13..23] ememr# eresdrv sden# iow# sa7 sa9 sa11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p2 10th center 30x2 berg amp 3-102977-0 ememw# gnd r225 1m dsma1 dsma3 dsma5 dsma7 dsmd1 dsmd3 dsma[0..14] dsmd[0..7] gnd dsma3 'a16(dacko#)' 'a14(dack7#)' 'cpuclk(pullup)' 'pullup(irq7)' 'lrdy#(drq6)' 'bhe#(irq9)' 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p4 10th center 30x2 berg amp 3-102977-0 dsma0 dsma2 dsma4 dsma6 dsmd2 dsmd4 'a15(dack3#)' 'a13(dack6#)' 'cpurst(rsvd)' 'rsvd(pullup)' 'ble#(irq11)' 'w/r#(drq7)' dsma[0..14] dsmd[0..7] gnd r224 1m vcc1 dsma0 iochrdy pgpc pgpa ld3 ld0 cp21 pirq0 pmc3 dsmd6 lvee# 'd/c#(drq0)' 'drq1' 'ioichchk#' 'pullup(irq10)' 'irq15' 'pgp2' 'pgp0' 'pirq0(irq3)' 'irq4' 'drq5' 'irq12' 'pullup' 'pgp3' 'pgp1' pmc4 pgpd pgpb lph# ld2 m1 frm1 cp11 dswe# dsmd5 dsmd7 epirq1 'm/io#(drq3)' 'ads#(ows#)' 'pulldn(irq5)' 'pir1(irq6)' pe a20gate pmc2 err# ack# 8042cs# slctin# ppdwe# memr# memw# sa1 sa3 sa5 memr# memw# '8042cs#[xtdat]' 'ppdwe#[ppdsc#]' busy init# rc# dack2# afdt# strb# slct ppoen# sa0 sa2 sa4 sa6 'dack2#[tck]' 'afdt#[x14out]' acin sout dtr# dsr# sin gnd resume# 'dtr#/cfg1' 'sus#/res#' gnd 'rts#/cfg0' smi rts# cts# dcd# ri# mcs16# jtagen eirq1 gnd 'irq1' iocs16# irq14 gnd elan signal headers note: elansc300 chip/schematic signal name 'ELANSC310 chip signal name'
date: march 29, 1996 sheet 4 of 23 size document number rev b elansc300/310 evaluation board 2.2 title xtal,switches,loop filter components,speaker amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. resdrv vccsys5 r385 67k resdrv tr 2 cv 5 q 3 dis 7 thr 6 r 4 v c c 8 u60 *555 timer r386 0 install this resistor & remove the 555 timer when using elan rev b3. eresdrv r391 *67k c241 *40pf eresdrv vcc5 11 10 1 4 u37e 74hct04(v5) gnd note: (elansc300 only) gnd gnd c236 *.01uf c237 *.1uf vccsys5 gnd c235 200pf when exiting upower off mode which could cause some issues. that is the reason for this one-shot. the 555 timer is configured to function as a one-shot. elansc300 revs b1 & b2 deliver a short resdrv pulse the elansc300 rev b3 device will address this issue & the one-shot is not needed. - elansc300 only - r17 0 c19 *0.47uf r15 0 c24 *0.47uf note elan pins to minimize trace length. place these componments close to the r16 0 c22 *0.47uf c18 *0.47uf lf2 lf3 lf1 lf4 lf1 lf2 lf3 lf4 r14 0 r21 0 c28 *0.47uf r19 0 c27 *0.47uf c32 *0.47uf note place these componments close to the elan socket pins to minimize trace length. r20 0 c30 *0.47uf slf1 slf2 slf3 slf4 slf1 slf2 slf3 slf4 r18 0 gnd video c29 0.47uf/5% pll pll low speed c26 0.47uf/5% pll intermediate c31 0.47uf/5% elansc300 pga socket loop filters pll high speed c33 0.47uf/5% gnd video c21 0.47uf/5% pll pll low speed c17 0.47uf/5% pll intermediate c23 0.47uf/5% elansc300/310 qfp chip loop filters pll high speed c25 0.47uf/5% gnd r384 *16m 1 4 2 3 x3 *32.768khz c233 *27pf c234 *27pf p32kinr p32kout 32khz crystal (pga) p32kin p32kinr p32kout r383 *33 bz1 buzzer(v5) spker spker resume# r11 33 r223 33 c200 0.1uf resume# vcc5 resrc# r10 100 c14 0.1uf resin# r381 0 1 2 d1 rls4148 r13 390k ovcc3 c20 2.2uf resin# r382 0 gnd reset switch sw2 sw pbno reset sw1 sw pbno sus/resume suspend/resume switch gnd gnd system speaker 32kin 32kout r216 33 32kinr 32kinr 32kout 32khz crystal (qfp) gnd c15 27pf c16 27pf 1 4 2 3 x1 32.768khz r12 16m
date: march 29, 1996 sheet 5 of 23 size document number rev b elansc300/310 evaluation board 2.2 title 33 mhz rpak option,mcs16# decode,baudout opt amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 33d[0..15] d[0..15] d8 d9 d10 d11 d12 d13 d14 d15 33d8 33d9 33d10 33d11 33d12 33d13 33d14 33d15 r310 0 r311 0 r312 0 r313 0 r314 0 r315 0 r316 0 r317 0 sa[13..23] vccsys5 mcs16# decode mcs16# r296 0 mcs16# aen r373 0 vccsys5 128k/64k# sa16 sa17 sa18 sa19 sa20 sa21 sa22 sa23 i1 1 i2 2 i3 3 i4 4 i5 5 i6 6 i7 7 i8 8 i9 9 i10 11 o1 19 o2 18 o3 17 o4 16 o5 15 o6 14 o7 13 o8 12 v c c 2 0 u50 *16l8-5 20-dip socket gnd r245 100k 1 2 jp22 *header 2 33d1 33d2 33d3 33d4 33d5 33d6 33d7 r318 0 r319 0 r320 0 r321 0 r322 0 r323 0 r324 0 r325 0 d1 d2 d3 d4 d5 d6 d7 d0 33d0 gnd 1 2 jp23 *header 2 place pal close to elan to minimize trace length on address lines. vccsys5 install jp22 & remove jp23 to enable mcs16# to addr ff0000-fffffe (64k) remove jp22 & jp23 to enable mcs16# to addr ffe000-fffffe (128k). ena/dis# r246 100k install jp23 to disable pal. * - indicates component removed from bill of material 33sa[12..23] 33sa23 r326 *0 r327 *0 sa23 sa[13..23] sa[0..12] sa13 sa14 sa15 sa16 sa17 sa18 sa19 sa20 sa21 sa22 33sa13 33sa14 33sa15 33sa16 33sa17 33sa18 33sa19 33sa20 33sa21 33sa22 r328 *0 r329 *0 r330 *0 r331 *0 r309 *0 r332 *0 r333 *0 r334 *0 r335 *0 r336 *0 afdt# r236 *0 baudout r237 0 14mout if using elansc300 rev a, always install r237 and depop r236. if using elansc300 rev b or ELANSC310 with the parallel port, install r237 and depop r236. if using elansc300 rev b or ELANSC310 without the parallel port, install r236 and depop r237. note: (only one resistor can be populated). srcs2# srcs3# srcs0# srcs1# srcs2# srcs3# srcs0# srcs1# 33sa12 r340 0 r337 *0 r338 *0 r339 *0 cas0l# cas0h# cas1l# cas1h# cas0l# cas0h# cas1l# cas1h# sa12 * - note: if using ELANSC310, do not populate r309 and r326 - r339. removing resistors will disable local bus video connector and sram sockets. depop resistors r309-r340 when running internal cga mode at 33 mhz to minimize capacitive loading on dram signals. elansc300 only: place resistors r309-r340 as close as possible to elan.
date: march 29, 1996 sheet 6 of 23 size document number rev b elansc300/310 evaluation board 2.2 title dram main memory simms amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. mwe# ras0# ras1# cas0l# cas0h# cas1l# cas1h# ras0# cas0l# mwe# vccdram vcc 1 cas 2 d1 3 a0 4 a1 5 d2 6 a2 7 a3 8 gnd 9 d3 10 a4 11 a5 12 d4 13 a6 14 a7 15 d5 16 a8 17 a9 18 a10 19 d6 20 we 21 gnd 22 d7 23 a11 24 d8 25 q9 26 ras 27 cas9 28 d9 29 vcc 30 p5 30pinsimm molex 15-46-3043 ma0 ma1 ma2 ma3 ma4 ma5 ras0# mwe# ma0 ma1 ma2 ma3 ma4 ma5 cas0h# vccdram vcc 1 cas 2 d1 3 a0 4 a1 5 d2 6 a2 7 a3 8 gnd 9 d3 10 a4 11 a5 12 d4 13 a6 14 a7 15 d5 16 a8 17 a9 18 a10 19 d6 20 we 21 gnd 22 d7 23 a11 24 d8 25 q9 26 ras 27 cas9 28 d9 29 vcc 30 p6 30pinsimm molex 15-46-3043 ras1# cas1l# mwe# ma0 ma1 ma2 ma3 ma4 ma5 vccdram vcc 1 cas 2 d1 3 a0 4 a1 5 d2 6 a2 7 a3 8 gnd 9 d3 10 a4 11 a5 12 d4 13 a6 14 a7 15 d5 16 a8 17 a9 18 a10 19 d6 20 we 21 gnd 22 d7 23 a11 24 d8 25 q9 26 ras 27 cas9 28 d9 29 vcc 30 p7 30pinsimm molex 15-46-3043 ras1# mwe# ma0 ma1 ma2 ma3 ma4 ma5 cas1h# vccdram vcc 1 cas 2 d1 3 a0 4 a1 5 d2 6 a2 7 a3 8 gnd 9 d3 10 a4 11 a5 12 d4 13 a6 14 a7 15 d5 16 a8 17 a9 18 a10 19 d6 20 we 21 gnd 22 d7 23 a11 24 d8 25 q9 26 ras 27 cas9 28 d9 29 vcc 30 p8 30pinsimm molex 15-46-3043 ras0# ras1# cas0l# cas0h# cas1l# vccdram vcc 10 vcc 30 vcc 59 ras0 44 ras1 45 ras2 34 ras3 33 cas0 40 cas1 43 cas2 41 cas3 42 we 47 a0 12 a1 13 a2 14 a3 15 a4 16 a5 17 a6 18 a7 28 a8 31 a9 32 a10 19 a11 29 d0 2 d1 4 d2 6 d3 8 d4 20 d5 22 d6 24 d7 26 d8 49 d9 51 d10 53 d11 55 d12 57 d13 61 d14 63 d15 65 d16 3 d17 5 d18 7 d19 9 d20 21 d21 23 d22 25 d23 27 d24 50 d25 52 d26 54 d27 56 d28 58 d29 60 d30 62 d31 64 prd1 67 prd2 68 nc 11 nc 35 nc 36 nc 37 nc 38 nc 46 nc 48 nc 66 nc 71 gnd 1 gnd 39 gnd 72 prd3 69 prd4 70 p9 72pinsimm molex 15-82-0762 mwe# ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 ma8 ma9 ma10 d0 cas1h# ma11 ma6 ma7 ma8 ma9 ma10 d8 d9 d10 d11 d12 d13 d14 d15 ma11 ma6 ma7 ma8 ma9 ma10 d0 d1 d2 d3 d4 d5 d6 d7 ma11 ma6 ma7 ma8 ma9 ma10 d0 d1 d2 d3 d4 d5 d6 d7 ma6 ma7 ma8 ma9 ma10 d8 d9 d10 d11 d12 d13 d14 d15 ma11 ma11 d[0..15] d[0..15] gnd gnd ma[0..11] gnd gnd d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 ma5 ma6 ma7 ma8 ma9 ma10 ma11 sa13 sa19 sa20 sa21 sa22 sa23 r31 0 r30 0 r32 0 r28 0 r26 0 r27 0 r29 0 sa12 r248 *0 sa[13..23] sa[13..23] sa[0..12] sa14 sa15 sa16 sa17 sa18 r22 0 r23 0 r24 0 r25 0 ma0 ma1 ma2 ma3 ma4 d15 gnd vccdram c36 0.1uf c38 0.1uf c39 0.1uf c40 0.1uf vccmem53 c34 10uf/10v c35 10uf/10v c37 0.1uf 1 2 jp7 header 2 power measurement point gnd gnd gnd gnd gnd gnd gnd main system memory - dram simms
date: march 29, 1996 sheet 7 of 23 size document number rev b elansc300/310 evaluation board 2.2 title sram main memory amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 33sa[12..23] 33d[0..15] sa[0..12] d[0..15] sa[0..12] 33sa[12..23] 33d8 33d9 33d10 33d11 33d12 33d13 33d14 33d15 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 i/o0 13 i/o1 14 i/o2 15 i/o3 17 i/o4 18 i/o5 19 i/o6 20 i/o7 21 a16 2 we 29 cs 22 a17 30 oe 24 gnd 16 vcc 32 a18 1 u3 *512kx8sram(mem53) 32-dip socket elansc300 only sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 33sa13 33sa12 33d0 33d1 33d2 33d3 33d4 33d5 33d6 33d7 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 33sa13 33sa12 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 i/o0 13 i/o1 14 i/o2 15 i/o3 17 i/o4 18 i/o5 19 i/o6 20 i/o7 21 a16 2 we 29 cs 22 a17 30 oe 24 gnd 16 vcc 32 a18 1 u2 *512kx8sram(mem53) 32-dip socket elansc300 only sa18cs r33 1k 33sa18 vccmem53 1 2 3 jp9 *header 3 3-pin jumper elansc300 only note: switch for 128kx8 or 512kx8 sram's srcs2# mwe# srcs2# sa18cs gnd 33sa14 33sa15 33sa16 33sa17 33sa19 gnd vccsram c42 0.33uf mwe# srcs3# sa18cs 33sa14 33sa15 33sa16 33sa17 33sa19 gnd vccsram c43 0.33uf gnd 33d8 33d9 33d10 33d11 33d12 33d13 33d14 33d15 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 i/o0 13 i/o1 14 i/o2 15 i/o3 17 i/o4 18 i/o5 19 i/o6 20 i/o7 21 a16 2 we 29 cs 22 a17 30 oe 24 gnd 16 vcc 32 a18 1 u5 *512kx8sram(mem53) 32-dip socket elansc300 only sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 33d0 33d1 33d2 33d3 33d4 33d5 33d6 33d7 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 3 a15 31 i/o0 13 i/o1 14 i/o2 15 i/o3 17 i/o4 18 i/o5 19 i/o6 20 i/o7 21 a16 2 we 29 cs 22 a17 30 oe 24 gnd 16 vcc 32 a18 1 u4 *512kx8sram(mem53) 32-dip socket elansc300 only srcs0# mwe# srcs0# sa18cs gnd 33sa13 33sa14 33sa15 33sa16 33sa17 33sa19 33sa12 gnd vccsram c44 0.33uf mwe# srcs1# sa18cs 33sa13 33sa14 33sa15 33sa16 33sa17 33sa19 33sa12 gnd vccsram c45 0.33uf gnd main system memory - sram * - note: if using ELANSC310, do not populate: u2 - u5, jp8, jp9 mwe# srcs3# srcs1# power measurement point vccmem53 1 2 jp8 *header 2 elansc300 only vccsram gnd c41 10uf/10v - elansc300 only -
date: march 29, 1996 sheet 8 of 23 size document number rev b elansc300/310 evaluation board 2.2 title scp, keyboard, mouse, & sd buffers amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. e d g e o f b o a r d 1 4 keyboard connector rc# 9 10 8 1 4 u48c 74hc32 vccsys5 irq1 a20gate msirq12 pmc4 pmc4 krc# r34 10k vcckbd5 gnd c46 0.1uf vcckbd5 ss 5 d6 18 p20 21 p21 22 p22 23 p23 24 p24/ob 35 p25/bf 36 t0 1 p26/drq 37 p10 27 p11 28 p12 29 p13 30 p14 31 p15 32 p16 33 v d d 2 6 v s s 2 0 p r o g 2 5 e a 7 d0 12 d1 13 d2 14 d3 15 d4 16 d5 17 reset 4 xtal2 3 xtal1 2 wr 10 rd 8 cs 6 a0 9 d7 19 sync 11 t1 39 p17 34 p27/dak 38 v c c 4 0 u6 80c42dip(sys5) 40-dip 1 2 jp10 header 2 vccsys5 vcckbd5 gnd c192 10uf/10v 1 2 jp30 *header 2 power measurement point sa[0..12] pclk 8042cs# xt keyboard sa[0..12] sa2 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 irq1 a20gate kbdclki kbdclko kbddato kbddati msdatao msclko msdatai msirq12 krc# kbclen# 1 2 d2 rls4148 vccsys5 5 6 1 4 u8c 74hct04(sys5) kbcl gnd vcckbd5 12 11 1 3 1 4 u7d 74hct125(kbd5) gnd gnd c47 0.1uf c52 0.1uf c53 2.2uf/6.3v c54 2.2uf/6.3v vcc5 vcc5 2 3 5 component side view 1 2 3 4 5 p10 5-pin din keyboard kbcl kbda gnd r36 1k gnd gnd r35 1k vcc5 c49 47pf c48 47pf kbda gnd vcckbd5 vcckbd5 9 8 1 0 1 4 u7c 74hct125(kbd5) r37 10k 1 2 d3 rls4148 vcckbd5 vccsys5 vccsys5 11 10 1 4 u8e 74hct04(sys5) 13 12 1 4 u8f 74hct04(sys5) kbddato# msdatao# msclki gnd vcc5 5 6 1 4 u37c 74hct04(v5) pclk 8042cs# iow# ior# vccsys5 1 2 3 1 4 u32a 74hct32(sys5) resdrv vcc5 9 8 1 4 u37d 74hct04(v5) kresdrv# gnd gnd msdatai msclko# r40 10k r41 10k 1 2 d4 rls4148 vccsys5 vcckbd5 vcckbd5 vcckbd5 3 4 1 4 u8b 74hct04(sys5) msda mscl 5 6 4 1 4 u7b 74hct125(kbd5) 2 3 1 1 4 u7a 74hct125(kbd5) msda mscl r38 1k r39 1k vcc5 1 2 3 4 5 6 p11 6-pin mini-din mouse vcc5 vcc5 gnd gnd gnd keyboard & mouse processor & connectors c51 47pf c50 47pf vccsys5 sd0 msclki vda 1 vdb 24 a0 3 b0 22 a1 4 b1 21 a2 5 b2 20 a3 6 b3 19 a4 7 b4 18 a5 8 b5 17 a6 9 b6 16 a8 11 b8 14 a7 10 b7 15 gnd 12 gnd 13 dir 2 g 23 u9 hd151015 24-soic vccb>=vcca 1 2 d5 rls4148 vccsys5 d0 svccmem53 pmc0 d1 d2 d3 d4 d5 d6 d7 gnd gnd r58 10k u9p11 gnd c174 0.1uf svccmem53 sd1 sd2 sd3 sd4 sd5 sd6 sd7 u9p14 bsdrdl bsden# sd0 sd1 sd2 sd3 gnd r59 10k c175 0.1uf gnd sd[0..15] sd[0..15] r45 1m r46 1m r47 1m r48 1m r49 1m vccsys5 (7,8,9,11,13,14,16,18) r42 1m r43 1m r44 1m r50 1m r51 1m r52 1m r53 1m r54 1m r55 1m r56 1m r57 1m sd4 sd5 sd6 sd7 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 vda 1 vdb 24 a0 3 b0 22 a1 4 b1 21 a2 5 b2 20 a3 6 b3 19 a4 7 b4 18 a5 8 b5 17 a6 9 b6 16 a8 11 b8 14 a7 10 b7 15 gnd 12 gnd 13 dir 2 g 23 u10 hd151015 24-soic vccb>=vcca u10p14 vccsys5 d8 d9 d10 d11 d12 d13 d14 d15 u10p11 gnd c176 0.1uf svccmem53 svccmem53 bsden# bsdrdl d[0..15] bsdrdh d[0..15] gnd gnd r61 10k bsdrdh bsden# gnd r60 10k gnd c177 0.1uf vccsys5 isa data bus level translating buffers
date: march 29, 1996 sheet 9 of 23 size document number rev b elansc300/310 evaluation board 2.2 title address buffering & rom connector amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. if using elansc300 rev a, always install jp31 on pins 2 & 3. if using elansc300 rev b or ELANSC310, then: install jp31 on pins 2 & 3 to select sa12. install jp31 on pins 1 & 2 to select a12, or note: (for local bus mode only). 33sa[12..23] 33sa12 1 2 3 jp31 *header 3 ma11/sa12 lvdd# lvdd# ELANSC310: 'a12(bale)' bsa0 elansc300 rev b: lvdd#(a12/bale) elansc300 rev a: lvdd#(bale) 1a1 2 1a2 4 1a3 6 1a4 8 2a1 11 2a2 13 2a3 15 2a4 17 1g 1 2g 19 1y1 18 1y2 16 1y3 14 1y4 12 2y1 9 2y2 7 2y3 5 2y4 3 vcc 20 gnd 10 u12 74act244 r349 33 r350 33 sa0 sa[0..12] sa[0..12] c178 0.1uf sa1 sa2 sa3 sa4 sa5 sa6 sa7 gnd vccsys5 gnd vccsys5 gnd 1a1 2 1a2 4 1a3 6 1a4 8 2a1 11 2a2 13 2a3 15 2a4 17 1g 1 2g 19 1y1 18 1y2 16 1y3 14 1y4 12 2y1 9 2y2 7 2y3 5 2y4 3 vcc 20 gnd 10 u13 74act244 r351 33 r352 33 r353 33 r354 33 r355 33 r356 33 r357 33 bsa1 bsa2 bsa3 bsa4 bsa5 bsa6 bsa7 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 vccsys5 gnd c180 0.1uf vccsys5 a12 or sa12 vda 1 vdb 24 a0 3 b0 22 a1 4 b1 21 a2 5 b2 20 a3 6 b3 19 a4 7 b4 18 a5 8 b5 17 a6 9 b6 16 a8 11 b8 14 a7 10 b7 15 gnd 12 gnd 13 dir 2 g 23 u14 hd151015 24-soic vccb>=vcca vla1 vla2 vla3 vla4 vla5 vla6 vla7 vla8 vla9 svccmem53 vla[1..12] vla[1..12] gnd c184 0.1uf svccmem53 vda 1 vdb 24 a0 3 b0 22 a1 4 b1 21 a2 5 b2 20 a3 6 b3 19 a4 7 b4 18 a5 8 b5 17 a6 9 b6 16 a8 11 b8 14 a7 10 b7 15 gnd 12 gnd 13 dir 2 g 23 u15 hd151015 24-soic vccb>=vcca gnd vla10 vla11 vla12 svccmem53 sa10 sa11 gnd vccsys5 bsa8 bsa9 bsa10 bsa11 bsa12 bsa21 bsa22 bsa23 gnd r358 33 r359 33 r360 33 r361 33 r362 33 r363 33 r364 33 sa8 sa9 sa10 sa11 sa12 gnd sa21 sa22 sa23 vccsys5 gnd vccsys5 c183 0.1uf sa[13..23] sa[13..23] sa13 sa14 sa15 sa16 sa17 sa18 sa19 sa20 gnd vccsys5 c179 0.1uf gnd vccsys5 gnd 1a1 2 1a2 4 1a3 6 1a4 8 2a1 11 2a2 13 2a3 15 2a4 17 1g 1 2g 19 1y1 18 1y2 16 1y3 14 1y4 12 2y1 9 2y2 7 2y3 5 2y4 3 vcc 20 gnd 10 u11 74act244 r365 33 r366 33 r367 33 r368 33 r369 33 r370 33 r371 33 r372 33 bsa14 bsa15 bsa16 bsa17 bsa18 bsa19 bsa20 bsa13 gnd gnd c181 0.1uf vccsys5 sdrdl sdrdh sden# gnd bsdrdl bsdrdh bsden# gnd c182 0.1uf svccmem53 local bus address translating buffers bsa[0..23] bsa[0..23] vccsys5 vccsys5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p12 *rom brd male hdr amp 1-104118-4 sd[0..15] sd[0..15] system address bus buffers o o o o o o o o o o o o o o o o o o o o o o e d g e o f b o a r d connector 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 sd0 sd2 sd4 sd6 sd8 sd10 sd12 sd14 bsa0 bsa2 bsa4 bsa6 sd1 sd3 sd5 sd7 sd9 sd11 sd13 sd15 bsa1 bsa3 bsa5 bsa7 bsa9 memw# mcs16# bromcs# bdoscs# gnd bsa11 bsa13 bsa15 bsa17 bsa19 bsa21 bsa23 memw# bromcs# bdoscs# bsa8 bsa10 bsa12 bsa14 bsa16 bsa18 bsa20 bsa22 memr# romvpp gnd sbhe# memr# romvpp sbhe# o o o o o o o o o o o o o o o o o o o o o o 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 o o o o o o o o 45 46 47 48 49 50 51 52 component side of board oo o o o o oo 53 54 55 56 57 58 59 60 note rom daughter card does full decoding depopulate roms on this board when using. connector (p12) is not standard on all boards and is only populated when needed. rom card connector
date: march 29, 1996 sheet 10 of 23 size document number rev b elansc300/310 evaluation board 2.2 title bios & dos rom (flash or eprom) amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. sd0 sd1 sd2 note: can place 128kx8 flash (28f010) in these sockets. a17 will not be used. sa0 sa1 sa2 alternate bios rom a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 dq0 13 dq1 14 dq2 15 dq3 17 dq4 18 dq5 19 dq6 20 dq7 21 a16 2 vpp 1 oe 24 a17 30 ce 22 gnd 16 vcc 32 we 31 u59 28f020a(sys5) 32-dip socket 28f010 sd0 sd1 sd2 bios rom a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 dq0 13 dq1 14 dq2 15 dq3 17 dq4 18 dq5 19 dq6 20 dq7 21 a16 2 vpp 1 oe 24 a17 30 ce 22 gnd 16 vcc 32 we 31 u20 28f020a(sys5) 32-dip socket 28f010 sa1 sa2 sa0 vccsys5 vccsys5 r250 1m 1 2 3 1 4 u52a 74act08 install jp24 and remove jp25 to enable bdoscs# as the chip select for rom bios accesses. remove jp24 and install jp25 to enable bromcs# during rom bios accesses. 1 2 jp24 *header 2 romcs# romcs# doscs# vccsys5 r249 1m doscs# bromcs# 1 2 jp25 *header 2 bdoscs# r301 0 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa13 bsa14 bsa15 bsa16 bsa17 bsa12 sd3 sd4 sd5 sd6 sd7 c59 0.1uf vccrom bsa12 bsa13 bsa14 bsa15 bsa16 bsa17 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sd3 sd4 sd5 sd6 sd7 vccrom c216 0.1uf vccsys5 bromcs2# memr# memw# gnd r300 1m gnd romvpp memw# romvpp memr# sd[0..15] bsa[0..23] sd[0..15] bsa[0..23] 1 2 3 jp32 header 3 bromcs1# bromcs2# bromcs# sa[0..12] dos roms: sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa13 sa[0..12] bsa12 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 a16 2 vpp 1 ce 22 a17 30 oe 24 gnd 16 vcc 32 a18 31 u16 27c040(sys5) 32-dip socket 28f020a sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa13 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 bsa12 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 a16 2 vpp 1 ce 22 a17 30 oe 24 gnd 16 vcc 32 a18 31 u17 27c040(sys5) 32-dip socket 28f020a sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa13 bsa12 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 a16 2 vpp 1 ce 22 a17 30 oe 24 gnd 16 vcc 32 a18 31 u18 *27c040(sys5) 32-dip socket sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa13 bsa12 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 a0 12 a1 11 a2 10 a3 9 a4 8 a5 7 a6 6 a7 5 a8 27 a9 26 a10 23 a11 25 a12 4 a13 28 a14 29 a15 3 o0 13 o1 14 o2 15 o3 17 o4 18 o5 19 o6 20 o7 21 a16 2 vpp 1 ce 22 a17 30 oe 24 gnd 16 vcc 32 a18 31 u19 *27c040(sys5) 32-dip socket gnd c58 0.1uf vccrom bsa14 bsa15 bsa16 bsa17 dos1cs# memr# romvpp romfls19 gnd c57 0.1uf vccrom bsa18 bsa14 bsa15 bsa16 bsa17 dos1cs# memr# romvpp romfls19 bsa18 bsa14 bsa15 bsa16 bsa17 memr# romvpp gnd c56 0.1uf vccrom bsa18 dos0cs# romfls19 gnd c55 0.1uf vccrom bsa14 bsa15 bsa16 bsa17 dos0cs# memr# romvpp romfls19 bsa18 memw# memr# romvpp note jumper 1 & 2 for flash parts jumper 2 & 3 for rom parts bsa19 romfls19 1 2 3 jp12 header 3 3-pin jumper memw# r308 33 dos0cs# dos1cs# vccsys5 a 2 b 3 g 1 y0 4 y1 5 y2 6 y3 7 v c c 1 6 u21a 74act139 r307 33 gnd 1 2 3 jp13 header 3 3-pin jumper bsa19 bsa20 dosah bdoscs# note jumper 1 & 2 for 256kx8 parts jumper 2 & 3 for 512kx8 parts 1 2 jp11 header 2 power measurement point vccsys5 gnd c193 10uf/10v vccrom gnd c194 10uf/10v or 256kx8 flash chips use switch for 512kx8 roms note bios & dos roms
date: march 29, 1996 sheet 11 of 23 size document number rev b elansc300/310 evaluation board 2.2 title c&t f87000 pcmcia buffers amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 1isa[0..25] 1isa0 1isa1 1isa2 1isa3 1isa4 1isa5 1isa6 1isa7 1isa8 1isa9 1isa[0..25] sa0 sa1 sa2 vccsys5 v c c 3 v c c 3 0 g n d 1 g n d 5 g n d 4 0 g n d 6 0 sa0 14 sa1 15 sa2 16 sa3 17 sa4 18 sa5 19 sa6 20 sa7 21 sa8 22 sa9 23 sa10 24 sa11 25 sa12 27 sa13 28 sa14 31 sa15 32 sa16 33 sa17 34 sa18 35 sa19 36 sa20 8 sa21 9 sa22 10 sa23 11 sa24 12 sa25 13 g n d 8 0 g n d 8 7 g n d 9 3 v c c 4 7 v c c 6 3 v c c 8 3 v c c 9 6 m o d e _ a 2 m o d e _ b 4 m o d e _ c 7 test 6 enaa 26 enab 29 or_in1 37 or_in2 38 c a _ a 0 1 0 0 c a _ a 1 9 8 c a _ a 2 9 7 c a _ a 3 9 5 c a _ a 4 9 4 c a _ a 5 9 2 c a _ a 6 9 1 ca_a7 90 ca_a8 73 ca_a9 71 ca_a10 69 ca_a11 70 ca_a12 88 ca_a13 75 ca_a14 77 ca_a15 85 ca_a16 82 ca_a17 72 ca_a18 74 ca_a19 76 ca_a20 78 ca_a21 79 ca_a22 81 ca_a23 84 ca_a24 86 ca_a25 89 cb_a0 68 cb_a1 67 cb_a2 66 cb_a3 65 cb_a4 64 cb_a5 62 cb_a6 61 cb_a7 59 cb_a8 44 cb_a9 42 cb_a10 39 cb_a11 41 cb_a12 57 cb_a13 46 cb_a14 49 cb_a15 55 cb_a16 53 cb_a17 43 c b _ a 1 8 4 5 c b _ a 1 9 4 8 c b _ a 2 3 5 4 c b _ a 2 4 5 6 c b _ a 2 5 5 8 c b _ a 2 0 5 0 c b _ a 2 1 5 1 c b _ a 2 2 5 2 or_out 99 u22 *c&tf87000m2(sys5) 100-pqfp elansc300 only sa[0..12] bsa[0..23] sa[0..12] bsa[0..23] vccsys5 1 2 4 5 6 1 4 u47a 74hc20 mce2# mce1# mce22# mce12# 1 2 3 1 4 u48a 74hc32 vccsys5 mce1# mce12# memr# mce2# mce22# memr# vccsys5 4 5 6 1 4 u45b 74hct08(sys5) vccsys5 1 2 3 1 4 u45a 74hct08(sys5) ena# enb# sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 bsa12 bsa13 bsa14 bsa15 bsa16 bsa17 1isa10 1isa11 1isa12 1isa13 1isa14 1isa15 1isa16 1isa17 1isa18 1isa19 1isa20 1isa21 1isa22 1isa23 1isa24 1isa25 2isa0 2isa1 2isa2 2isa3 2isa4 2isa5 2isa6 2isa7 2isa8 2isa9 2isa10 2isa11 2isa12 isa24 isa25 bsa18 bsa19 bsa20 bsa21 bsa22 bsa23 r62 100k vccsys5 bena# benb# isa24 isa25 enb# ena# 1 2 3 jp34 *header 3 elansc300 only 4 5 6 1 4 u48b 74hc32 ememr# vccsys5 r238 *0 ememw# elansc300 rev a or elansc300 rev b with parallel port. solder down u48 pins 3 and 6 and depop r238 & r239 if using lift (disconnect) u48 pins 3 and 6, and populate r238 & r239 note: r239 *0 memw# memw# r374 100k r375 100k 1 2 3 jp35 *header 3 elansc300 only u21p37 vccsys5 vccsys5 r259 100k r260 100k gnd 2isa13 2isa14 2isa15 2isa16 2isa17 2isa18 2isa19 2isa20 2isa21 2isa22 2isa23 2isa24 2isa[0..25] 2isa[0..25] 1mce1# 1mce2# 1icreg# 2mce1# 2mce2# 1isd[0..15] vccsys5 r221 10k 2isa25 r220 10k mce1# mce12# reg1# mce2# mce22# 1a1 2 1y1 18 1a2 4 1y2 16 1a3 6 1y3 14 1a4 8 1y4 12 2a1 11 2y1 9 2a2 13 2y2 7 2a3 15 2y3 5 2a4 17 2y4 3 vcc 20 gnd 10 1g 1 2g 19 u24 *74hct244(sys5) 20-soic elansc300 only 1isd0 1isd1 1isd2 1isd3 1isd4 1isd5 1isd6 1isd[0..15] (1,2,3) (1,2,3) (1,2,3) (1,2,3) (1,2,3) vccsys5 v c c 3 v c c 3 0 g n d 1 g n d 5 g n d 4 0 g n d 6 0 sd0 36 sd1 35 sd2 34 sd3 33 sd4 32 sd5 31 sd6 29 sd7 28 sd8 27 sd9 26 sd10 25 sd11 24 sd12 23 sd13 22 sd14 21 sd15 20 g n d 8 0 g n d 8 7 g n d 9 3 v c c 4 7 v c c 6 3 v c c 8 3 v c c 9 6 m o d e _ a 2 m o d e _ b 4 m o d e _ c 7 test 6 cardaon 16 cardbon 17 or_in1 41 or_in2 39 ca_d0 82 ca_d1 85 ca_d2 88 ca_d3 70 ca_d4 72 ca_d5 74 ca_d6 76 ca_d7 78 ca_d8 81 ca_d9 84 ca_d10 86 ca_d11 71 ca_d12 73 ca_d13 75 ca_d14 77 ca_d15 79 cb_d0 65 cb_d1 67 cb_d2 69 cb_d3 52 cb_d4 54 cb_d5 56 cb_d6 58 cb_d7 61 cb_d8 64 cb_d9 66 cb_d10 68 cb_d11 53 cb_d12 55 cb_d13 57 cb_d14 59 cb_d15 62 or_out 99 icdir 10 iow 12 ior 13 oe0 19 reg 11 we0 18 c a _ i o w 9 4 c a _ i o r 9 2 c a _ w e 9 5 c a _ o e 9 1 c a _ r e g 9 8 c b _ i o w 4 6 c b _ i o r 4 5 c b _ w e 4 8 c b _ o e 4 4 c b _ r e g 5 0 c a _ i o i s 1 6 1 0 0 c b _ i o i s 1 6 5 1 c b _ w a i t 4 9 c a _ w a i t 9 7 c a _ c e 1 8 9 c a _ c e 2 9 0 c b _ c e 1 4 2 c b _ c e 2 4 3 iois16 37 wait 38 mcce1 8 mcce2 9 enaa 15 enab 14 u23 *c&tf87000m3(sys5) 100-pqfp elansc300 only sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sd8 sd[0..15] sd[0..15] pmc1 pmc3 ememr# ememw# ememr# ememw# pmc1 pmc3 if using elansc300 rev b without parallel port, or ELANSC310. also see note on page 15. if using ELANSC310, do not populate u22-u24, u49, jp34, jp35. vccsys5 vccsys5 vccsys5 r251 100k r252 100k r253 100k sd9 sd10 sd11 sd12 sd13 sd14 sd15 vccsys5 r214 100k vccsys5 r254 100k 1isd7 1isd8 1isd9 1isd10 1isd11 1isd12 1isd13 1isd14 1isd15 2isd0 2isd1 2isd2 2isd3 2isd[0..15] (1,2,3) reg2# gnd vccsys5 vccsys5 ena# 4 5 6 1 4 u46b 74hct32(sys5) pmc1 pmc3 u42p12 2icreg# 2isd[0..15] wait# vcc5 12 13 11 1 4 u42d 74hct08(v5) u42p13 pcmcia buffers - elansc300 only vccsys5 enb# wait1# wait2# 1 2 3 1 4 u46a 74hct32(sys5) 2isd4 2isd5 2isd6 2isd7 2isd8 2isd9 2isd10 2isd11 2isd12 2isd13 2isd14 2isd15 pmc1 pmc3 vccsys5 vccsys5 bena# benb# r63 100k 9 8 1 4 u8d 74hct04(sys5) icdir r295 100k vccsys5 vccsys5 r294 100k pmemr# pmemw# ior# iow# gnd vccsys5 1a1 2 1y1 18 1a2 4 1y2 16 1a3 6 1y3 14 1a4 8 1y4 12 2a1 11 2y1 9 2a2 13 2y2 7 2a3 15 2y3 5 2a4 17 2y4 3 vcc 20 gnd 10 1g 1 2g 19 u49 *74hct244(sys5) 20-soic elansc300 only u22p41 1imemr# 1imemw# 1ixior# 1ixiow# 2imemr# 2imemw# 2ixior# 2ixiow# pmc1 pmc3 gnd rev1.2-pins 8&9 of u23 change from mce1# & mce2# to mce12# & mce22# r255 100k r256 100k vccsys5 vccsys5 gnd gnd gnd gnd gnd gnd gnd gnd c60 0.1uf c61 0.1uf c62 0.1uf c63 0.1uf c64 0.1uf c65 0.1uf c66 0.1uf c67 0.1uf vccsys5 vccsys5 see note (above-left) for elansc300/310 rework.
date: march 29, 1996 sheet 12 of 23 size document number rev b elansc300/310 evaluation board 2.2 title buffered pcmcia connectors amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 1 2 3 1 4 u53a 74hc32 cd1# vcc5 vcc5 r79 10k pcd1# pcd12# r265 10k 1isd11 1isd12 1isd13 gnd pcd1# vcc1crd5 1isd3 1isd4 1isd5 1isd6 vcc1crd5 gnd gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1 7 a10 8 oe 9 a11 10 a9 11 a8 12 a13 13 a14 14 we 15 rdy/ireq 16 vcc 17 vpp1 18 a16 19 a15 20 a12 21 a7 22 a6 23 a5 24 a4 25 a3 26 a2 27 a1 28 a0 29 d0 30 d1 31 d2 32 wp/iois 33 gnd 34 gnd 35 cd1 36 d11 37 d12 38 d13 39 d14 40 d15 41 ce2 42 rfsh 43 nior 44 niow 45 a17 46 a18 47 a19 48 a20 49 a21 50 vcc 51 vpp2 52 a22 53 a23 54 a24 55 a25 56 nc 57 reset 58 wait 59 inpack 60 reg 61 bvd2/spk 62 bvd1/sts 63 d8 64 d9 65 d10 66 cd2 67 gnd 68 p14 *ic card amp 175649-2 elansc300 only 1isd[0..15] 1mce1# 1isd[0..15] icvpp1 1imemr# 1imemw# rdy1# vcc1crd5 c70 10uf/16v r69 10k icvpp1 1mce1# 1imemr# 1imemw# 1isd7 1isa10 1isa11 1isa9 1isa8 1isa13 1isa14 1isa16 1isa15 rdy1# 1mce2# 1ixior# 1ixiow# 1isd14 1isd15 1isa22 1isa23 1isa17 1isa18 1isa19 1isa20 1isa21 r80 10k vcc1crd5 r82 10k r81 10k 1mce2# 1ixior# 1ixiow# 27 28 29 30 31 32 33 34 61 62 63 64 65 66 67 68 ic card connector amp 175649-2 1icrst 1icreg# bvd11 bvd12 wait1# r269 1m 1icrst 1isa24 1isa25 wait1# 1icreg# 1isd8 1isd9 1isd10 pcd12# bvd12 bvd11 gnd 1isa0 1isa2 1isa1 1isa3 1isa4 1isa5 1isa6 1isa7 1isd0 1isd1 1isd2 1isa12 gnd wp1 gnd gnd gnd vcc1crd5 vcc2crd5 r302 1m r303 1m wp1 2isd[0..15] 1isa[0..25] 1isa[0..25] 2isd[0..15] r83 10k vcc1crd5 gnd vcc2crd5 vcc2crd5 gnd vcc5 r77 10k r266 10k pcd2# vcc5 gnd e d g e o f b o a r d 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 35 36 37 38 39 40 41 42 43 44 45 component 2mce2# 2ixior# 2ixiow# 4 5 6 1 4 u53b 74hc32 cd2# pcd22# 2mce2# 2ixior# 2ixiow# 2isd11 2isd12 2isd13 2isd14 2isd15 2isa17 2isa18 2isa19 pcd2# 2mce1# 2imemr# 2isd3 2isd4 2isd5 2isd6 2isd7 2isa10 2isa11 2isa9 2isa8 2isa13 2isa14 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1 7 a10 8 oe 9 a11 10 a9 11 a8 12 a13 13 a14 14 we 15 rdy/ireq 16 vcc 17 vpp1 18 a16 19 a15 20 a12 21 a7 22 a6 23 a5 24 a4 25 a3 26 a2 27 a1 28 a0 29 d0 30 d1 31 d2 32 wp/iois 33 gnd 34 gnd 35 cd1 36 d11 37 d12 38 d13 39 d14 40 d15 41 ce2 42 rfsh 43 nior 44 niow 45 a17 46 a18 47 a19 48 a20 49 a21 50 vcc 51 vpp2 52 a22 53 a23 54 a24 55 a25 56 nc 57 reset 58 wait 59 inpack 60 reg 61 bvd2/spk 62 bvd1/sts 63 d8 64 d9 65 d10 66 cd2 67 gnd 68 p13 *ic card amp 175649-2 elansc300 only vcc2crd5 r67 10k 2imemr# 2mce1# 2imemw# rdy2# icvpp2 gnd c71 10uf/16v 2isa0 2isa1 2isa2 2isa3 2isa4 2isa5 2isa7 2isa6 2imemw# 2isa16 2isa15 2isa12 rdy2# 2icrst 2isa24 2isa25 wait2# 2icreg# 2isa20 2isa21 2isa22 2isa23 r78 10k bvd22 bvd21 vcc2crd5 r75 10k r76 10k bvd22 2icreg# bvd21 2icrst wait2# side view pcmcia buffered connectors gnd r272 1m 2isd8 2isd9 2isd10 pcd22# gnd 2isd0 2isd1 2isd2 gnd wp2 2isa[0..25] vcc2crd5 r65 10k wp2 2isa[0..25] if using ELANSC310, do not populate p13 and p14. vcc2crd5 gnd vcc1crd5 gnd c68 10uf/10v c69 10uf/10v - elansc300 only -
date: march 29, 1996 sheet 13 of 23 size document number rev b elansc300/310 evaluation board 2.2 title non-buffered pcmcia connectors amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. nbcd1# pcd1# 2 3 d6 rb400d vcc5 r92 10k gnd sd11 sd12 sd13 nbcd1# vcc1crd5 vcc1crd5 gnd sd3 sd4 sd5 sd6 gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1 7 a10 8 oe 9 a11 10 a9 11 a8 12 a13 13 a14 14 we 15 rdy/ireq 16 vcc 17 vpp1 18 a16 19 a15 20 a12 21 a7 22 a6 23 a5 24 a4 25 a3 26 a2 27 a1 28 a0 29 d0 30 d1 31 d2 32 wp/iois 33 gnd 34 gnd 35 cd1 36 d11 37 d12 38 d13 39 d14 40 d15 41 ce2 42 rfsh 43 nior 44 niow 45 a17 46 a18 47 a19 48 a20 49 a21 50 vcc 51 vpp2 52 a22 53 a23 54 a24 55 a25 56 nc 57 reset 58 wait 59 inpack 60 reg 61 bvd2/spk 62 bvd1/sts 63 d8 64 d9 65 d10 66 cd2 67 gnd 68 p16 *ic card amp 175649-2 elansc300 only sd[0..15] sd[0..15] mce12# icvpp1 rdy1# icvpp1 sd7 sa10 sa11 sa9 sa8 mce12# bsa13 bsa14 bsa16 bsa15 pmemr# pmemw# rdy1# sd14 sd15 ior# iow# mce1# bsa17 bsa18 bsa19 bsa20 bsa21 bsa22 bsa23 ior# iow# mce1# 27 28 29 30 31 32 33 34 61 62 63 64 65 66 67 68 ic card connector amp 175649-2 1icrst bvd11 bvd12 isa24 isa25 reg1# wait1# 1icrst wait1# sd8 sd9 sd10 isa25 isa24 reg1# bvd12 bvd11 gnd pcd12# gnd sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sd0 sd1 sd2 wp1 bsa12 sa[0..12] sa[0..12] pmemr# wp1 pmemw# gnd vcc2crd5 vcc2crd5 gnd vcc5 r93 10k nbcd2# e d g e o f b o a r d 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 1 2 3 4 5 6 7 8 9 10 11 35 36 37 38 39 40 41 42 43 44 45 component mce2# pcd2# 2 3 d7 rb400d sd11 sd12 sd13 sd14 sd15 ior# iow# mce2# nbcd2# bsa17 bsa18 bsa19 mce22# sd3 sd4 sd5 sd6 sd7 sa10 sa11 sa9 sa8 bsa13 bsa14 pmemr# gnd 1 d3 2 d4 3 d5 4 d6 5 d7 6 ce1 7 a10 8 oe 9 a11 10 a9 11 a8 12 a13 13 a14 14 we 15 rdy/ireq 16 vcc 17 vpp1 18 a16 19 a15 20 a12 21 a7 22 a6 23 a5 24 a4 25 a3 26 a2 27 a1 28 a0 29 d0 30 d1 31 d2 32 wp/iois 33 gnd 34 gnd 35 cd1 36 d11 37 d12 38 d13 39 d14 40 d15 41 ce2 42 rfsh 43 nior 44 niow 45 a17 46 a18 47 a19 48 a20 49 a21 50 vcc 51 vpp2 52 a22 53 a23 54 a24 55 a25 56 nc 57 reset 58 wait 59 inpack 60 reg 61 bvd2/spk 62 bvd1/sts 63 d8 64 d9 65 d10 66 cd2 67 gnd 68 p15 *ic card amp 175649-2 elansc300 only mce22# rdy2# icvpp2 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 bsa16 bsa15 pmemw# rdy2# bsa12 2icrst wait2# isa24 isa25 reg2# bsa20 bsa21 bsa22 bsa23 bvd22 bvd21 bvd22 bvd21 2icrst reg2# wait2# side view pcmcia non-buffered connectors sd8 sd9 sd10 gnd pcd22# gnd sd0 sd1 sd2 wp2 bsa[0..23] wp2 bsa[0..23] if using ELANSC310, do not populate p15 and p16. - elansc300 only -
date: march 29, 1996 sheet 14 of 23 size document number rev b elansc300/310 evaluation board 2.2 title display sram & crt & lcd connectors amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. d9 ir detector bpv22f r107 21.5k 2 1 3 q2 mmbr5179l vcc5 vcc5 2 1 3 q1 mmbr5179l r108 21.5k c82 0.01uf r109 10k r110 100k gnd vcc5 gnd siri r112 21.5k vcc5 vcc5 3 2 1 8 4 u27a lf353(v5) d8 ir led f1000-80034 vcc5 vcc5 siro siri clk1 1 clk2 13 i1 2 i2 11 i3 14 i4 23 i/o1 22 i/o2 21 i/o3 20 i/o4 19 i/o5 18 i/o6 17 i/o7 16 i/o8 15 i/o9 3 i/o10 4 i/o11 5 i/o12 6 i/o13 7 i/o14 8 i/o15 9 i/o16 10 gnd 12 vcc 24 u28 *palce610(v5) 24-dip socket not populated r113 21.5k r114 21.5k r115 21.5k vcc5 vcc5 vcc5 sin sout pmc2 baudout gnd c83 1uf/10v gnd r111 6.81k/1% gnd serial infra-red circuit gnd dsmd[0..7] dsmd[0..7] vccsy253 dsmd0 dsmd1 dsmd2 dsmd3 dsmd4 dsmd5 dsmd6 dsmd7 sdsmd0 sdsmd1 sdsmd2 sdsmd3 sdsmd4 sdsmd5 sdsmd6 sdsmd7 place r341-r348 close to u25. r341 *33 r344 *33 r343 *33 r342 *33 r345 *33 r346 *33 r347 *33 r348 *33 dsma0 dsma1 dsma2 dsma3 dsma4 dsma5 dsma6 dsma7 dsma8 dsma9 dsma10 dsma11 dsma12 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 1 ce 20 oe 22 we 27 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 vcc 28 gnd 14 u25 *62256-10(sys253) 28-dip 32kx8 sram toshiba dsma[0..14] dsce# dsoe# dswe# encga# dsma[0..14] encga# vccsy253 1 2 3 1 4 u26a 74hct32(sys253) dsma13 dsma14 sramcs# gnd c72 *0.1uf if using ELANSC310, do not populate: u25, r341-r348, p17, p18, c72-81, r95-r106, vr1. internal video ram - elansc300 only - ld3 ld0 frm1 ld2 cp11 ld1 cp21 gnd 5 9 4 8 3 7 2 6 1 p17 *cga crt amp 747844-4 ld1 ld2 ld3 cp11 cp21 m1 frm1 gnd c73 *330pf r101 *15 r102 *15 r99 *15 r100 *15 r97 *15 r98 *15 r95 *15 r96 *15 c74 *330pf c75 *330pf c76 *330pf c77 *330pf lcdfrm lcdcp1 lcdcp2 lcdm lcdd0 lcdd1 lcdd2 vcclcd5 c78 *330pf c80 *330pf c79 *330pf gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p18 *lcd conn 10th cntr 20x1 berg amp 2-102976-0 1 2 3 6 7 e d g e o f b o a r d cga crt connector vcclcd5 4 5 8 9 component side view - elansc300 only - lcdd3 lcdd10 lcdd11 lcdd12 lcdd13 vee contrast vcclcd5 r94 *220k 1 3 2 vr1 *20k bourns 3590 r105 *15 r106 *15 r103 *15 r104 *15 rev1.2-change ld0,ld1,ld2,ld3 to ld1,ld2,ld3,ld0 ld0 iocs16# mcs16# irq14 sbhe# vee contrast c81 *0.1uf internal video lcd & crt connectors
date: march 29, 1996 sheet 15 of 23 size document number rev b elansc300/310 evaluation board 2.2 title serial & parallel port circuits & conns amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. side view e d g e o f b o a r d connector serial 3 4 5 7 8 9 5 9 4 8 3 7 2 6 1 p19 serial amp 747840-4 sin1 sout1 dcd1# dsr1# rts1# sin1r sout1r dcd1r# dsr1r# rts1r# r122 300 r124 300 r125 300 r126 300 r127 300 r128 300 r116 1m ro3 21 ro2 22 ro4 20 di2 23 di3 19 ro1 24 di1 25 ro5 18 ri3 9 ri2 8 ri4 10 do3 11 ri1 6 do1 5 ri5 12 on/off 13 c1+ 3 c1- 4 c2+ 27 c2- 26 v+ 1 v- 28 5v 2 gnd 17 do2 7 u30 lt1337a(v5) 28-wsoic r117 1m r118 1m r119 1m r120 1m vcc5 sin sout dcd# dsr# rts# cts# dtr# ri# pmc2 vcc5 2 3 d23 rb400d c116 1uf/16v gnd c92 0.1uf srpvpls srpc1p srpc1m c115 1uf/16v cts1r# dtrx1r# ri1r# srpc2p srpc2m srpvm gnd gnd r121 300 r123 300 c113 1uf/16v c114 1uf/16v c87 220pf c88 220pf c89 220pf c90 220pf c91 220pf gnd gnd gnd gnd gnd cts1# dtrx1# ri1# c84 220pf c85 220pf c86 220pf gnd gnd gnd gnd component side view 1 2 6 serial port interface 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 p20 printer amp 747846-4 ppstrb# ppafdt# ppinit# ppslctn# pd0 pd1 pd2 pd3 pd4 pd5 pperr# c101 220pf gnd c102 220pf c103 220pf c104 220pf gnd gnd gnd r129 47 r130 47 r131 47 r132 47 pmemw# r145 4.7k r146 4.7k r240 *0 r143 4.7k r144 4.7k vcc5 ememw# pmemr# init# strb# afdt# slctin# ememr# r242 *0 ppoen# slctin# without parallel port. elansc300 rev b with parallel port. populate r242 & r240 and depop r243 & r241 if using elansc300 rev a or populate r243 & r241 and depop r242 & r240 if using elansc300 rev b if using ELANSC310, depopulate all 4 resistors: r240 - r243. r243 *0 pages 5 and 11. also see notes on init# r241 *0 sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 le 11 gnd 10 vcc 20 u29 74hc373(v5) pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 c93 220pf c110 0.1uf vcc5 c94 220pf c95 220pf c96 220pf c97 220pf pd6 pd7 ppack# ppbusy c98 220pf c99 220pf c100 220pf pppe ppslct gnd connector 1 14 parallel gnd gnd gnd gnd gnd gnd gnd pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd[0..7] gnd gnd vcc5 sd0 sd1 sd2 sd3 sd4 sd5 sd6 vda 1 vdb 24 a0 3 b0 22 a1 4 b1 21 a2 5 b2 20 a3 6 b3 19 a4 7 b4 18 a5 8 b5 17 a6 9 b6 16 a8 11 b8 14 a7 10 b7 15 gnd 12 gnd 13 dir 2 g 23 u31 hd151015 24-soic vccb>=vcca vccsys5 ppclkr gnd c112 0.1uf vccsys5 vcc5 11 12 13 1 4 u41d 74hct02(v5) ppdwe# iow# sd[0..15] ior# sd[0..15] vccsys5 4 5 6 1 4 u32b 74hct32(sys5) pprd# sd7 gnd pd7 gnd gnd pprd# c111 0.1uf r138 4.7k r139 4.7k r140 4.7k r141 4.7k vcc5 r142 4.7k vcc5 e d g e o f b o a r d 2 3 4 5 6 7 8 9 15 16 17 18 19 20 21 component side view 10 11 12 13 22 23 24 25 gnd c105 220pf c106 220pf c107 220pf c108 220pf gnd gnd gnd c109 220pf r133 47 r134 47 r135 47 r136 47 r137 47 gnd err# busy pe ack# slct parallel port interface
date: march 29, 1996 sheet 16 of 23 size document number rev b elansc300/310 evaluation board 2.2 title isa bus connectors amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. sd[0..15] sd[0..15] sd1 sd2 sd3 sd4 sd5 sd6 sd7 iochchk# gnd 50 resdrv 51 +5v 52 irq9 53 -5v 54 dreq2 55 -12v 56 -0ws 57 +12v 58 gnd 59 -smemw 60 -smemr 61 -iow 62 -ior 63 -dack3 64 dreq3 65 -dack1 66 dreq1 67 -refsh 68 sysclk 69 irq7 70 irq6 71 irq5 72 irq4 73 irq3 74 -dack2 75 tc 76 ale 77 +5v 78 14.3mhz 79 gnd 80 -iochck 1 d7 2 d6 3 d5 4 d4 5 d3 6 d2 7 d1 8 d0 9 iochrdy 10 aen 11 a19 12 a18 13 a17 14 a16 15 a15 16 a14 17 a13 18 a12 19 a11 20 a10 21 a9 22 a8 23 a7 24 a6 25 a5 26 a4 27 a3 28 a2 29 a1 30 a0 31 -sbhe 32 sa23 33 la22 34 la21 35 la20 36 la19 37 la18 38 la17 39 -memr 40 -memw 41 sd8 42 sd9 43 sd10 44 sd11 45 sd12 46 sd13 47 sd14 48 sd15 49 -memcs16 81 -iocs16 82 irq10 83 irq11 84 irq12 85 irq15 86 irq14 87 -dack0 88 dreq0 89 -dack5 90 dreq5 91 -dack6 92 dreq6 93 -dack7 94 dreq7 95 +5v 96 -master 97 gnd 98 p22 isa at conn amp 645169-3 irq9 vccsys5 resdrv drq2 m5volt m12volt m5volt m12volt 0ws# gnd gnd 50 resdrv 51 +5v 52 irq9 53 -5v 54 dreq2 55 -12v 56 -0ws 57 +12v 58 gnd 59 -smemw 60 -smemr 61 -iow 62 -ior 63 -dack3 64 dreq3 65 -dack1 66 dreq1 67 -refsh 68 sysclk 69 irq7 70 irq6 71 irq5 72 irq4 73 irq3 74 -dack2 75 tc 76 ale 77 +5v 78 14.3mhz 79 gnd 80 -iochck 1 d7 2 d6 3 d5 4 d4 5 d3 6 d2 7 d1 8 d0 9 iochrdy 10 aen 11 a19 12 a18 13 a17 14 a16 15 a15 16 a14 17 a13 18 a12 19 a11 20 a10 21 a9 22 a8 23 a7 24 a6 25 a5 26 a4 27 a3 28 a2 29 a1 30 a0 31 -sbhe 32 sa23 33 la22 34 la21 35 la20 36 la19 37 la18 38 la17 39 -memr 40 -memw 41 sd8 42 sd9 43 sd10 44 sd11 45 sd12 46 sd13 47 sd14 48 sd15 49 -memcs16 81 -iocs16 82 irq10 83 irq11 84 irq12 85 irq15 86 irq14 87 -dack0 88 dreq0 89 -dack5 90 dreq5 91 -dack6 92 dreq6 93 -dack7 94 dreq7 95 +5v 96 -master 97 gnd 98 p21 isa at conn amp 645169-3 sd1 sd2 sd3 sd4 sd5 sd6 sd7 iochchk# irq9 drq2 resdrv m5volt m12volt 0ws# gnd vccsys5 dack3# drq3 dack1# drq1 irq7 irq5 smemr# smemw# pclk p12volt pirq1 ior# iow# gnd vccsys5 sd0 aen iochrdy bsa13 bsa14 bsa15 bsa16 bsa17 bsa18 bsa19 bsa12 bsa11 bsa10 bsa9 bsa8 pclk pirq1 ior# iow# p12volt p12volt vccsys5 dack3# drq3 dack1# drq1 irq7 irq5 sd0 bsa13 bsa14 bsa15 bsa16 bsa17 bsa18 bsa19 bsa12 bsa11 bsa10 bsa9 bsa8 iochrdy aen bsa[0..23] bsa[0..23] sbhe# la20 la21 la22 la23 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 irq4 irq10 irq11 irq12 gnd bale vccsys5 tc iocs16# mcs16# pirq0 14mout dack2# la20 la21 la22 la23 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 gnd sbhe# irq4 irq10 irq11 irq12 iocs16# mcs16# bale tc pirq0 14mout dack2# vccsys5 irq15 dack0# dack5# dack6# dack7# drq0 drq5 drq6 drq7 irq14 gnd vccsys5 sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 memr# memw# la17 la18 la19 irq14 vccsys5 irq15 dack0# dack5# dack6# dack7# drq0 drq5 drq6 drq7 gnd sd8 sd9 sd10 sd11 sd12 sd13 sd14 sd15 la17 la18 la19 gnd 1 2 3 jp33 *header 3 memw# memr# lmeg# memr# memw# elmeg# smemr# smemw# vccsys5 12 13 11 1 4 u32d 74hct32(sys5) 9 10 8 1 4 u32c 74hct32(sys5) r232 1k vcc1 0ws# dsma[0..14] dsma4 dsma5 dsma6 dsma7 dsma8 dsma9 dsma10 dsma11 dsma12 dsma1 dsma[0..14] dack6# dack7# dack3# dack0# la17 la18 la19 la20 la21 irq7 1 2 s1 short 1 2 s2 short 1 2 s3 short 1 2 s4 short 1 2 s5 short 1 2 s6 short 1 2 s7 short 1 2 s8 short 1 2 s30 short 1 2 s31 short 1 2 s32 short irq4 irq5 234567891 0 1 1 1 2 1 3 1 4 1 rp1 10k socket amp 643646-2 vccsys5 vcc1 234567891 0 1 1 1 2 1 3 1 4 1 rp3 *10k socket amp 643646-2 elansc300 only encga# enflisa# enlocal vcc1 dtr# rts# gnd dswe# 23456789 1 0 1 1 1 2 1 3 1 4 1 rp4 *10k socket amp 643646-2 elansc300 only if using ELANSC310, depopulate rp3 and rp4. drq5 drq1 drq0 drq3 drq7 drq6 irq7 irq9 irq10 irq11 irq12 irq15 iochchk# la22 la23 dack1# drq1 dack5# drq5 iochchk# irq4 irq5 lmeg# bale 1 2 s9 short 1 2 s10 short 1 2 s11 short 1 2 s12 short 1 2 s13 short 1 2 s14 short 1 2 s15 short 1 2 s16 short 1 2 s17 short 1 2 s18 short 1 2 s19 short dsma13 dsma14 ld0 ld1 ld2 ld3 m1 cp11 dsoe# dsce# lvdd# dsmd[0..7] cp21 frm1 lvee# dsmd1 dsmd2 dsmd3 dsmd4 dsmd5 dsmd6 dsmd7 dsmd[0..7] dsmd0 drq6 irq11 irq9 drq7 drq3 drq0 irq10 irq12 irq15 0ws# 1 2 s20 short 1 2 s21 short 1 2 s23 short 1 2 s24 short 1 2 s25 short 1 2 s26 short 1 2 s27 short 1 2 s28 short 1 2 s29 short 'ldev#(rsvd)' 'ELANSC310 chip signal name' 23456789 1 0 1 1 1 2 1 3 1 4 1 rp2 10k socket amp 643646-2 note: layout isa & vl-bus connectors according to spec. (in line, 0.5 inch spacing). gnd isa bus interface
date: march 29, 1996 sheet 17 of 23 size document number rev b elansc300/310 evaluation board 2.2 title vl-bus & local bus vga connectors amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. gnd svccmem53 gnd vlcpuclk vla23 gnd vla21 vla22 vla13 vla14 vla15 vla16 vla17 vla18 vla19 vla20 vccmem53 vccmem53 vccmem53 vlcpurst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p24 vga conn 30x2 hirose fx660p0.8sv2 gnd svccmem53 o o o o o o o o o o o o o o e d g e o f b o a r d connector 2 4 6 8 vga 10 11 12 13 14 1 3 5 7 9 note: pin 1 indicator on local bus connector is really pin 2 in our design. vee o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o vgalvee# 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 vcc5 vlm/io# vlads# vlbhe# vlw/r# vgardy# vlble# vlldev# vee resdrv vla1 vla2 vla3 vla4 vla5 vla6 vla7 vla8 vla9 vla10 vla11 vla12 vcc5 vcc5 33d10 33d12 33d14 33d11 33d15 33d13 vcc5 resdrv vla[1..12] 33d[0..15] d[0..15] vla[1..12] gnd gnd gnd gnd 33d0 33d2 33d4 33d6 33d8 33d1 33d3 33d5 33d7 33d9 vcc1 component side of board o o o o o o o o o o o o o o oo 234567891 0 1 1 1 2 1 3 1 4 1 rp5 10k socket amp 643646-2 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vlna# vlldev# vlrdyi# vlbusy# vlpreq drq1 irq4 irq12 irq15 387err# iochchk# dtr# rts# note dtr# pulled up & encga# enflisa# enlocal vlcpurst 1 2 14 u33a 74hct04(mem53) svccmem53 forces local bus mode in elan. rts# pulled down sout note: in local bus mode, cpu clock = 1x in local bus mode, cpu clock = 2x sout pulled up sout pulled down (not supported). gnd drq5 1 2 3 jp16 header 3 3-pin jumper gnd r151 100k vcc5 23456789 1 0 1 1 1 2 1 3 1 4 1 rp6 10k socket amp 643646-2 dsma[0..14] dsma[0..14] dsma4 dsma5 dsma6 dsma7 dsma8 dsma9 dsma10 dsma11 dsma12 dsma13 vla13 vla14 vla15 vla16 vla17 vla18 vla19 vla20 vla21 vla22 dsma1 dsma2 dsma3 vlna# vlcpurst vlcpuclk 1 2 s36 short 1 2 s37 short 1 2 s38 short 1 2 s39 short 1 2 s40 short 1 2 s41 short 1 2 s42 short 1 2 s43 short 1 2 s44 short 1 2 s45 short 1 2 s46 short 1 2 s47 short 1 2 s48 short 1 2 s49 short 1 2 3 4 8 7 6 5 sw3 sw dip-4 dsma14 vla23 vlrdyo# vlpreq vlbusy# 387err# drq1 drq5 iochchk# irq4 irq12 irq15 1 2 s50 short 1 2 s51 short 1 2 s52 short 1 2 s53 short 1 2 s54 short 1 2 s55 short 1 2 s56 short 1 2 s57 short 1 2 s58 short 1 2 s59 short cp11 cp21 dsoe# dswe# ld0 ld2 ld3 m1 frm1 lvee# dsmd[0..7] dsmd6 dsmd7 dsmd0 dsmd1 dsmd2 dsmd3 dsmd4 dsmd5 dsmd[0..7] vlble# vlbhe# vlw/r# vlm/io# vld/c# vlads# vlldev# vlrdyi# 1 2 s60 short 1 2 s61 short 1 2 s62 short 1 2 s63 short 1 2 s64 short 1 2 s65 short 1 2 s66 short 1 2 s67 short note switch in vlbrdyi# to use the vl bus. switch in vgardy# to use the vga connector switch in vlrdyo# if the vga card needs it. vgardy# vlrdyo# vlrdyi# local bus interface
date: june 6, 1996 sheet 18 of 23 size document number rev b elansc300/310 evaluation board 2.2 title dc/dc power amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. m12volt 1 2 jp37 *header 2 resin# op12volt 1 2 jp36 *header 2 r147 *330 gnd gnd gnd c119 0.1uf c125 10uf/16v c124 10uf/16v gnd gnd c120 0.1uf 1 2 3 4 5 6 p25 pc power conn burndy gtc6r-1 1 2 3 4 5 6 p26 pc power conn burndy gtc6r-1 op12volt pm12volt lvee# gnd gnd c122 0.1uf c127 10uf/10v pm5volt gnd gnd c121 0.1uf c126 10uf/10v op5volt note vee is controlled by vgalvee# in local bus mode. vee is off in isa bus mode. vee is controlled by lvee# in internal cga mode. vcc5 2 3 1 1 4 u41a 74hct02(v5) vcc5 vcc5 8 9 10 1 4 u41c 74hct02(v5) 3 4 1 4 u37b 74hct04(v5) op5volt p5volt gnd r388 100k m5volt 2 1 3 q24 pmbt3904 r277 1.5k r387 100k gnd r389 100k r276 10k 4 1 5 23 8 67 q23 si9430dy op12volt p12volt 2 4 1 7 8 5 6 3 q26 si9956dy ovcc3 r280 1m gnd c242 *10uf/20v gnd 4 3 5 1 2 q25 fmc2 r279 0 c206 *0.1uf p5volt op12volt d18 *3.6v 1w add wire: r228 50k 2.) cut short shape s108 3.) add wire: to connect u40 pin 9 1.) remove components: l1 and d18. to 'op5volt' (cathode side of d18). rework instructions: regulation when in suspend mode). (to correct 3.3 volt (vcc3) output vcc5 5 6 4 1 4 u41b 74hct02(v5) vcc5 vcc5 1 2 1 4 u37a 74hct04(v5) encga# enlocal vgalvee# r159 100k ovcc3 r283 100k lx3 15 cs+ 9 cs- 10 dhi 11 dlow 12 fbn 8 vref 5 pfo 4 gnd 14 agnd 6 v+ 16 shdn 1 negon 2 3/5 3 fb3 7 lin 13 u40 max722 envee r161 1m r154 100k ovcc3 gnd gnd bat cx130 75uf/6.3v c130 75uf/6.3v gnd r155 1 4 5 23 8 67 q6 si9400dy 1 2 s108 *short l1 *22uh/1a 1 2 d10 1n5817 gnd c129 100uf/6.3v ovcc3 gnd gnd vcc3 r376 1m gnd c243 *10uf/10v gnd vee vee gnd c128 2.2uf/30v gnd 1 2 d11 1n5818 l2 47uh/0.25a r157 1.5m/1% r156 470 r160 110k/1% c131 0.22uf gnd c123 0.1uf r158 330 1 2 3 q3 2n2955 1 2 d13 rlr4001 resdrv# vccsys5 1 2 14 u8a 74hct04(sys5) resdrv vcc1 r233 10k vcc5 vcc5 d 2 q 5 clk 3 q 6 p r 4 c l 1 v c c 1 4 u39a 74hct74(v5) p12volt gnd gnd p5volt op12volt 4 3 5 1 2 q27 fmc2 gnd r281 0 r282 1m c207 *0.1uf 2 4 1 7 8 5 6 3 q28 si9956dy vccmem53 svccmem53 1 2 sot-23 rb400d r o h m 3 gnd c244 *10uf/10v romvpp icvpp1 icvpp2 4 1 5 23 8 67 q5 si9430dy p-mosfet 2 3 d12 rb400d vcc5 vcc5 vccsys5 gnd 2 1 3 q4 pmbt3904 p12volt r152 1.5k r153 1m vdd 14 vppin 4 en21 8 en20 9 en10 12 low2 10 gnd 6 nc 2 vppo1 1 vppo2 7 vcc1 3 vcc2 5 low1 13 en11 11 u36 *mic2558(v5) 14-soic elansc300 only sd2 pgpa vcc5 vcc5 d 2 q 5 clk 3 q 6 p r 4 c l 1 v c c 1 4 u38a *74hct74(v5) elansc300 only sd1 sd2 pgpa vcc5 pgpa vpp1 vpp2 sd[0..15] sd[0..15] sd0 pgpa vcc5 if using ELANSC310, depopulate u36 and u38. d 12 q 9 clk 11 q 8 p r 1 0 c l 1 3 v c c 1 4 u38b *74hct74(v5) elansc300 only resdrv# vpp1 vpp2 gnd p12volt gnd gnd gnd c117 0.1uf c118 0.1uf power supply
date: march 29, 1996 sheet 19 of 23 size document number rev b elansc300/310 evaluation board 2.2 title xioreset#,p5volt generation amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. d24 led p5volt on/off indicator op5volt d 2 q 5 clk 3 q 6 p r 4 c l 1 v c c 1 4 u55a 74hc74 d 12 q 9 clk 11 q 8 p r 1 0 c l 1 3 v c c 1 4 u54b 74hc74 op5volt d 2 q 5 clk 3 q 6 p r 4 c l 1 v c c 1 4 u54a 74hc74 op5volt op5volt 1 2 1 4 u62a 74act14 3 4 1 4 u62b 74act14 op5volt sw5 sw pbno r284 100k on/off switch gnd c238 .1uf r390 0 ras0# op12volt r288 4.7k gnd r304 300 gnd 2 1 3 q29 pmbt3904 r287 1k 1 2 1 4 u57a 74hc04 op5volt 1 2 3 1 4 u56a 74hc08 op5volt 1 2 3 1 4 u58a 74hc32 gnd op5volt c208 1uf r285 100k gnd op5volt r286 10k op5volt c245 10uf/10v 1 2 jp26 *header 2 4 5 2 678 3 q31 si9410dy op5volt p5volt 4 5 2 678 3 q30 si9410dy op5volt gnd c210 0.1uf gnd r290 1m 5 6 1 4 u62c 74act14 9 8 1 4 u62d 74act14 4 5 6 1 4 u56b 74hc08 op5volt op5volt r392 33 1 2 jp27 *header 2 remove jp27 if using elansc300 rev b or ELANSC310 without upower mode. xioreset# gnd c209 1uf r289 1m p5volt install jp26 to disable micropower. remove jp26 to enable micropower circuitry. gnd micro power mode switch
date: march 29, 1996 sheet 20 of 23 size document number rev b elansc300/310 evaluation board 2.2 title power switching amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. origin of vcc3 gnd r377 0 c228 *0.1uf r378 1m 2 4 1 7 8 5 6 3 q37 si9956dy gnd 4 3 5 1 2 q36 fmc2a 2 3 d16 rb400d vcc5 vcc5 vccsy253 vcc5 vccsys5 2 3 d15 *rb400d gnd c254 0.01uf tant gnd c255 0.01uf tant vcc5 vccsys5 vcc1 2 3 d14 rb400d gnd c253 0.01uf tant vccmem53 gnd c251 0.01uf tant gnd c252 0.01uf tant vcc1 vccsy253 p5volt enlocal sw_mem53 r189 47k sw_mem35 op5volt 4 5 6 1 4 u35b 74hct32 4 3 5 1 2 q32 fmc2a 4 3 5 1 2 q34 fmc2a gnd 2 4 1 7 8 5 6 3 q33 si9956dy r292 0 c214 *0.1uf r293 1m r305 0 2 4 1 7 8 5 6 3 q35 si9956dy vcc1 plane vcc3 p5volt gnd c246 33uf tant vcc1 l7 1.2uh origin of vccsy253 plane vccsy253 c247 33uf tant gnd l8 1.2uh p5volt r170 0 2 4 1 7 8 5 6 3 q7 si9956dy gnd c215 *0.1uf r306 1m p12volt 4 3 5 1 2 q19 fmc2a gnd acin bl1# bl2# bl3# bl4# c145 0.1uf gnd vcc5 r188 33 r186 10k r187 10k r180 100 r181 100 r182 100 r183 100 r179 100k r178 10k op5volt r184 10k r185 10k irq1 pirq1 gnd sw_mem53 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sw4 sw dip-8 sw_bl1# sw_bl2# sw_bl3# sw_bl4# sw_acin eirq1 epirq1 epirq1 eirq1 pirq1 irq1 enflisa# install jp28 on pins 1&2 if using micropower to keep dram powered up encga# c144 0.1uf gnd enflisa# c140 0.1uf c141 0.1uf c142 0.1uf gnd gnd vcc5 9 10 8 1 4 u42c 74hct08(v5) encga# c143 0.1uf gnd gnd p5volt 4 3 5 1 2 q17 fmc2a gnd r167 1m r169 1m c132 *0.1uf r172 0 2 4 1 7 8 5 6 3 q9 si9956dy origin of ovcc3 vccmem53 vccmem53 plane op5volt c248 33uf tant gnd l9 1.2uh gnd r166 1m c134 *0.1uf r173 0 c135 *0.1uf 2 4 1 7 8 5 6 3 q10 si9956dy gnd sw_mem35 4 3 5 1 2 q16 fmc2a op5volt 1 2 3 jp28 *header 3 op12volt install jp28 on pins 2&3 if not using micropower or if while in upower off mode. dram is not required to be powered up in upower off mode. pmc1 p12volt nbcd1# vcc5 4 5 6 1 4 u42b 74hct08(v5) p12volt vcc5 4 3 5 1 2 q22 *fmc2a elansc300 only gnd r164 1m r175 4.7k c137 0.1uf 2 4 1 7 8 5 6 3 q11 *si9956dy elansc300 only vcc1crd5 origin of vcc1crd5 plane vcc5 gnd p12volt p5volt sw_mem35 4 3 5 1 2 q18 fmc2a gnd gnd r168 1m c133 *0.1uf r171 0 2 4 1 7 8 5 6 3 q8 si9956dy origin of p5volt vcc5 vcc5 plane l10 1.2uh power switching c249 33uf tant gnd gnd r165 1m r174 0 c136 *0.1uf 2 4 1 7 8 5 6 3 q14 si9956dy p12volt gnd p5volt 4 3 5 1 2 q15 fmc2a vcc2crd5 origin of vcc2crd5 plane vcc5 gnd r162 1m c138 0.1uf r176 4.7k 2 4 1 7 8 5 6 3 q12 *si9956dy elansc300 only p12volt vcc5 4 3 5 1 2 q21 *fmc2a elansc300 only vcc5 1 2 3 1 4 u42a 74hct08(v5) pmc3 nbcd2# lvdd# encga# vccsy253 4 5 6 1 4 u26b 74hct32(sys253) p12volt vccsy253 if using ELANSC310, remove q11-q13 and q20-q22. 4 3 5 1 2 q20 *fmc2a elansc300 only gnd r163 1m r177 0 c139 *0.1uf 2 4 1 7 8 5 6 3 q13 *si9956dy elansc300 only vcclcd5 vcc5 l11 1.2uh origin of 3 4 5 fmc2a sot-25 rohm vccsys5 vccsys5 plane c250 33uf tant gnd 1 2
date: march 29, 1996 sheet 21 of 23 size document number rev b elansc300/310 evaluation board 2.2 title floppy & ide interface amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. connector fdd berg vccsys5 r150 10k sio1sin sio1sout sio1rts# sio1dtr# sio1cts# sio1dsr# sio1dcd# sio1ri# sa[0..12] sa[0..12] sa0 sa1 sa2 sa3 sa4 gnd gnd c148 0.1uf c149 0.1uf c150 0.1uf gnd vccsys5 x2 8 x1/osc 7 mr 2 aen 20 a0 30 a1 29 a2 28 a3 27 a4 26 a5 25 a6 24 a7 23 a8 22 a9 21 d0 17 d1 16 d2 15 d3 14 d4 13 d5 12 d6 11 d7 10 rd 19 wr 18 iochrdy/mfm 53 zws/csout/pwdn 3 irq3 1 irq4 100 irq5 98 irq6 97 irq7 96 tc 6 drq 4 dack 5 ideack/ident 54 v c c a 3 3 v c c 5 0 v c c 9 9 v s s a 3 1 g n d 9 g n d 4 2 g n d 6 1 g n d 9 0 rdata 35 wdata 39 wgate 38 hdsel 34 dir 41 step 40 trk0 37 index 47 dskchg 32 wp 36 mtr0 46 mtr1 43 dr0 44 dr1 45 drv2/pnf 49 densel 48 s i n 1 7 5 s i n 2 6 7 s o u t 1 / b o t 1 / c f g 3 7 3 s o u t 2 / b o t 2 / c f g 0 6 5 r t s 1 / c f g 4 7 4 r t s 2 / c f g 1 6 6 d t r 1 / c f g 2 7 1 d t r 2 / v l d 1 6 3 c t s 1 7 2 c t s 2 6 4 d s r 1 7 6 d s r 2 6 8 d c d 1 7 7 d c d 2 6 9 r i 1 7 0 r i 2 6 2 pd0/index 94 pd1/trk0 93 pd2/wp 92 pd3/rdata 91 pd4/dskchg 89 pd5/msen0 88 pd6 87 pd7/msen1 86 slin/step/astrb 81 stb/write 95 afd/dstrb/dense 78 init/dir 80 ack/dr1 85 err/hdsel 79 slct/wgate 82 pe/wdata 83 busy/wait/mtr1 84 h c s 0 / p o e # 5 8 h c s 1 / p d i r 5 7 i d e d 7 6 0 i d e h i / v l d o # 5 6 i d e l o / b a d d r 0 5 5 i o c s 1 6 5 9 drate0/msen0 52 drate1/msen1 51 u43 pc87322vf(sys5) national super i/o flpindx# flpdchg flpdir# flpstep# flpwrd# r190 1k r191 1k r192 1k r193 1k vccsys5 r194 1k r195 1k r196 1k o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o e d g e o f b o a r d 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 o o o o component side of board 31 32 33 34 flpdensl flpdrt0 r197 *1k r198 *1k flpwe# flptrk0# flpwp# flprdd# flphds# flpds0# flpme0# flpdrt0r flpdensr flpds1# flpme1# sd0 sd1 sd2 sd3 sd4 sd5 sd6 sd7 sa5 sa6 sa7 sa8 sa9 sd[0..15] sd[0..15] resdrv pirq1 drq2 dack2# tc ior# iow# aen iochrdy resdrv dack2# tc drq2 ior# iow# sioirq3 index 8 drvsel 14 dchng 34 - - - 4 - - - 12 motor 10 dir 18 gnd 13 step 20 gnd 15 gnd 17 gnd 19 gnd 21 gnd 23 gnd 25 wdata 22 wgate 24 track0 26 wp 28 rdata 30 side 32 densel 2 drate0 6 gnd 1 - - - 3 gnd 5 gnd 7 gnd 9 gnd 11 gnd 27 gnd 29 gnd 31 gnd 33 motor 16 p27 fdd 10th cntr 17x2 berg amp 1-102977-7 r230 1k r231 1k vccsys5 o o o o o o o o o o o o o o o o o o e d g e o f b o a r d ide hdd connector 12 34 56 78 910 11 12 13 14 15 16 17 18 gnd r222 1k gnd gnd c146 27pf 1 2 x2 24mhz r200 1m flp24x2 vccsys5 r149 10k note uart for interrupt choose mouse or 1 2 3 jp17 header 3 pirq0 msirq12 resdrv# frm1 vcc1 r229 100k 1 2 jp18 header 2 note populate to use mouse in full isa mode flp24x1 sd5 sd6 ided7 c147 27pf gnd reset 1 data7 3 data6 5 data5 7 data4 9 data3 11 data2 13 data1 15 data0 17 gnd 19 - - - 21 iow 23 ior 25 (iocrdy) 27 - - - 29 irq 31 addr1 33 addr0 35 cs0 37 hddacc 39 gnd 2 data8 4 data9 6 data10 8 data11 10 data12 12 data13 14 data14 16 data15 18 (vcc) 20 gnd 22 gnd 24 gnd 26 (ale) 28 gnd 30 iocs16 32 pdiag 34 addr2 36 cs1 38 gnd 40 vcclgc 41 vccmtr 42 type 44 gnd 43 p28 ide 10th cntr 22x2 berg amp 2-102977-2 sd8 sd9 sd10 o o o o o o o o o o o o o o o o o o o o o o o o o o 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 component side of board sd11 sd12 sd13 sd14 sd15 sa2 r199 10k vccsys5 vccsys5 r217 0 sd0 sd1 sd2 sd3 sd4 sa0 sa1 ior# iow# gnd 9 10 8 1 4 u46c 74hct32(sys5) vccsys5 irq14 gnd 1 2 s104 short pgpb iocs16# gnd u46p13 1 2 s107 short pgpc 12 13 11 1 4 u46d 74hct32(sys5) vccsys5 vccsys5 gnd gnd gnd c195 10uf/10v vccsys5 super i/o floppy & ide hard drive
date: march 29, 1996 sheet 22 of 23 size document number rev b elansc300/310 evaluation board 2.2 title spare gates & super i/o serial port amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p38 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p35 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p42 10th ctr hole grid vcc5 d 12 clk 11 q 9 q 8 v c c 1 4 p r 1 0 c l 1 3 u39b 74hct74(v5) 1 2 s85 short 1 2 s86 short 1 2 s87 short u39p10 u39p11 u39p12 vcc5 gnd 12 13 11 1 4 u48d 74hc32 vccsys5 1 2 s115 short 1 2 s116 short u33p5 1 2 s71 short 5 6 1 4 u33c 74hct04(mem53) svccmem53 1 2 s88 short u39p13 vcc5 u37p13 vcc5 13 12 1 4 u37f 74hct04(v5) gnd 1 2 s78 short u33p9 u33p11 1 2 s72 short 1 2 s73 short 9 8 1 4 u33d 74hct04(mem53) 11 10 1 4 u33e 74hct04(mem53) svccmem53 svccmem53 gnd u33p13 1 2 s74 short 13 12 1 4 u33f 74hct04(mem53) svccmem53 u35p2 u35p1 1 2 s101 short 1 2 s100 short op5volt 1 2 3 1 4 u35a 74hct32 vcc5 vcc5 5 6 7 8 4 u27b lf353(v5) grid of 10th center holes for board updates gnd gnd 1 g1 con1 gnd point berg header 1 g2 con1 gnd point berg header gnd gnd gnd 1 g3 con1 gnd point berg header 1 g4 con1 gnd point berg header 1 g5 con1 gnd point berg header u27p7 gnd 9 10 12 13 8 1 4 u47b 74hc20 vccsys5 1 2 s109 short 1 2 s110 short op5volt op5volt 9 10 8 1 4 u35c 74hct32 12 13 11 1 4 u35d 74hct32 1 2 s83 short 1 2 s84 short u35p9 u35p10 1 2 s89 short 1 2 s90 short u35p12 u35p13 vccsy253 vccsy253 gnd 12 13 11 1 4 u26d 74hct32(sys253) 9 10 8 1 4 u26c 74hct32(sys253) 1 2 s79 short 1 2 s80 short 1 2 s81 short 1 2 s82 short gnd u26p9 u26p10 u26p12 u26p13 gnd 1 2 s97 short 1 2 s98 short 1 2 s99 short vccsys5 u21p14 u21p15 u21p13 vccsys5 a 14 b 13 g 15 y0 12 y1 11 y2 10 y3 9 v c c 1 6 u21b 74act139 1 2 s111 short 1 2 s112 short gnd e d g e o f b o a r d connector serial spare gates gnd ground posts for debug 1 g6 con1 gnd point berg header component side view 1 2 3 4 5 6 7 8 9 5 9 4 8 3 7 2 6 1 p45 serial amp 747840-4 sin2 sout2 dcd2# dsr2# rts2# cts2# dtrx2# ri2# r206 300 r207 300 r208 300 r209 300 r210 300 r211 300 r212 300 r213 300 sin2r sout2r dcd2r# dsr2r# rts2r# cts2r# dtrx2r# ri2r# r201 1m r202 1m r203 1m r204 1m ro3 21 ro2 22 ro4 20 di2 23 di3 19 ro1 24 di1 25 ro5 18 ri3 9 ri2 8 ri4 10 do3 11 ri1 6 do1 5 ri5 12 on/off 13 c1+ 3 c1- 4 c2+ 27 c2- 26 v+ 1 v- 28 5v 2 gnd 17 do2 7 u44 lt1337a(sys5) 28-wsoic sio1dcd# sio1dsr# sio1sin sio1rts# sio1sout sio1cts# sio1dtr# sio1ri# r205 1m vccsys5 gnd pmc2 c159 0.1uf c161 1uf/16v vccsys5 2 3 d25 rb400d c160 1uf/16v gnd gnd c162 1uf/16v c163 1uf/16v c156 220pf c157 220pf c158 220pf gnd gnd gnd c151 220pf c152 220pf c153 220pf c154 220pf c155 220pf gnd gnd gnd gnd gnd gnd super i/o serial interface
date: march 29, 1996 sheet 23 of 23 size document number rev b elansc300/310 evaluation board 2.2 title spares continued amd proprietary/all rights reserved (800) 222-9323 austin, texas 78741 5204 e. ben white blvd. (c) advanced micro devices, inc. vccsys5 1 2 s118 short op5volt 1 2 s120 short 1 2 s121 short gnd d 12 q 9 clk 11 q 8 p r 1 0 c l 1 3 v c c 1 4 u55b 74hc74 1 2 s119 short op5volt 9 10 8 1 4 u56c 74hc08 12 13 11 1 4 u56d 74hc08 1 2 s122 short 1 2 s123 short 1 2 s124 short op5volt op5volt vcc5 vcc5 1 2 s137 short 1 2 s138 short 1 2 s139 short 9 10 8 1 4 u53c 74hc32 12 13 11 1 4 u53d 74hc32 1 2 s141 short 1 2 s142 short 1 2 s143 short vccsys5 4 5 6 1 4 u52b 74act08 9 10 8 1 4 u52c 74act08 1 2 s145 short vccsys5 12 13 11 1 4 u52d 74act08 1 2 s144 short 1 2 s146 short 1 2 s140 short gnd 1 2 s125 short gnd op5volt 1 2 s126 short op5volt 4 5 6 1 4 u58b 74hc32 5 6 1 4 u57c 74hc04 1 2 s133 short op5volt gnd 9 8 1 4 u57d 74hc04 1 2 s134 short 11 10 1 4 u57e 74hc04 1 2 s135 short op5volt op5volt op5volt 9 10 8 1 4 u58c 74hc32 1 2 s127 short 1 2 s128 short 1 2 s129 short 1 2 s130 short 1 2 s131 short gnd 12 13 11 1 4 u58d 74hc32 gnd op5volt 13 12 1 4 u57f 74hc04 1 2 s136 short op5volt 1 2 s151 short 11 10 1 4 u62e 74act14 op5volt gnd op5volt c240 0.1uf 13 12 1 4 u62f 74act14 op5volt place caps close to device that it belongs to. decoupling caps for components that i added on the rev 2.2 design. 1 2 s152 short gnd gnd gnd vccsys5 vcc5 c221 0.1uf c222 0.1uf gnd gnd gnd vccsys5 vccsys5 vccsys5 c219 0.1uf c220 0.1uf gnd gnd vccsys5 c217 0.1uf c218 0.1uf 3 4 1 4 u33b 74hct04(mem53) svccmem53 1 2 s102 short gnd u33p3 gnd op5volt decoupling caps for components that i added on the rev 2 design. place caps close to device that it belongs to. c223 0.1uf c224 0.1uf gnd gnd gnd op5volt op5volt op5volt c225 0.1uf c226 0.1uf gnd op5volt c227 0.1uf
1.0 lansc310 microcontroller evaluation board users manual index-1 numerics 8042 keyboard controller, 2-20, 4-14 a acin pin related to pmu, 3-9 simulating battery back-up conditions, 2-25 application rom booting from in phoenixpico, 2-12 displaying region, 3-12 interface, using 8- or 16-bit, 3-12 memory mapping, 4-9 restrictions, 2-5 size, selecting, 2-22 supported, xi writes, enabling, 4-5 b battery backup, simulation, 2-25 level, related to pmu, 3-9 bios options for phoenixpico, 2-11C2-15 options for systemsoft, 2-6C2-9 overview, 2-5 phoenixpico bios, 2-10C2-15 phoenixpico diskette, 3-1 restrictions, 2-4 shadowing in systemsoft, 2-8 supported, xi systemsoft bios, 2-6C2-9 systemsoft diskette, 3-1 bios rom displaying region, 3-12 memory mapping, 4-9 selecting, 2-22 writes, enabling, 4-5 bioscs , 4-9 bl1 Cbl4 , 2-24 booting boot sector writes in systemsoft, 2-7 diskette, from, 1-2C1-7 fast boot in systemsoft, 2-7 first boot in systemsoft, 2-7 order in phoenixpico, 2-12 setting password in systemsoft, 2-8 breadboard area, 2-24 bus modes jumper settings to select, a-2 overview, 2-16 restrictions, 2-4 selecting, 2-17 supported, xi see also local bus, isa bus, and video bus. index evalbd.book : evalbd.ix page 1 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-2 1.0 c clk setting in phoenixpico, 2-13 com ports, internal setting in systemsoft, 2-7 configuration jumpers, a-2 connectors, external, x cpurdy , 2-18 cs1 , 4-3 d datalight diskette, 3-1 debugging, supported, xi disk drive selecting type in phoenixpico, 2-11 selecting type in systemsoft, 2-6 dma mapping, 4-13 dos booting from a diskette, 1-2C1-7 dos rom see application rom. doze mode changing from in systemsoft, 2-9 forcing, 3-8 power management, in, 2-24 setting in elanpmu, 3-7 dram installing, 2-19 restrictions, 2-4 e elan pmu evaluation utility see elanpmu. elaninit.zip, 3-2 elanpmu, 3-4C3-9 elanpmu.zip, 3-3 lansc310 evaluation board see evaluation board. eprom address mapping, 4-6 programming, 4-5C4-7 restrictions, 2-4 selecting, 2-22 errata, 1-2 evalset serial and parallel port setup utility see evalset.exe. evalset.exe examples, 3-11 using, 3-10C3-11 evalset.zip, 3-3 evaluation board avoiding damage to, 1-2 components of, 4-14C4-15 features, xCxi installation requirements, 1-3 installing, 1-4C1-5 jumpers and switches, listing of, 2-3 layout diagram, 2-2 layout suggestions, c-1Cc-2 overview, ix quick start, 1-1 restrictions, 2-4C2-5 setup summary, a-1Ca-4 troubleshooting, 1-6C1-7 exiting phoenixpico setup screen, 2-15 systemsoft setup screen, 2-9 extended memory see memory, extended. evalbd.book : evalbd.ix page 2 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-3 1.0 f flash address mapping, 4-6 initialization example, 4-7 jumper settings, 4-6 programming, 3-3, 4-5C4-7 restrictions, 2-4 selecting, 2-22 flash.exe, 3-3 flash.zip, 3-3 h hard drive ide, see ide hard drive. setting parameters in systemsoft, 2-6, 2- 11 high speed mode changing from in systemsoft, 2-8 power management, in, 2-24 restrictions, 2-5 toggling between it and suspend, 2-25 high speed pll mode, 3-6 i i/o interfaces integrated, 2-20C2-21 map, 4-10C4-11 overview, 2-20 ports, accessing from command line, 3-4 ide hard drive connecting, 1-7C1-8 connection location, 2-21 interface, 4-15 index 48h, 4-15 index 51h, 4-6 index 62h, 4-5 index 62h, 4-5 index 65h, 4-8, 4-9 index 69h, 4-8 index 6dh, 4-8 index 70h, 4-2 index 74h, 4-3 index 77h, 4-15 index 80h, 4-4 index 81h, 4-4 index 89h, 4-2, 4-10 index 91h, 4-2, 4-3 index 92h, 4-15 index 94h, 4-3 index 9ch, 4-3 index ach, 4-4 index b8h, 4-9 index registers accessing from command line, 3-4 initialization example, 3-2 installing board, 1-4C1-5 requirements, 1-3 troubleshooting, 1-6C1-7 irq mapping, 4-11 irq1, 2-25 irq12, 2-20 irq4, 2-21 isa bus mode overview, 2-17 restrictions, 2-4 j jp10, a-4 jp11, a-4 jp12, 2-22, a-2 jp13, 2-22, a-2 jp16, a-2 evalbd.book : evalbd.ix page 3 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-4 1.0 jp16Cjp18, 2-17 jp17, 2-20, a-2 jp18, 2-20, a-2, a-3 jp19, 2-23, a-4 jp1Cjp11, 2-23 jp1Cjp7, a-4 jp32, 2-5, 2-22, a-2 jumpers configuration, a-2 power measurement, a-4 settings, a-1 l layout of board, 2-2 local bus card using, 2-18 local bus mode, 2-18 low speed mode changing from in systemsoft, 2-8 power management, in, 2-24 low speed pll mode forcing, 3-8 setting in elanpmu, 3-7 lrdy , 2-18 m memory board, on, x extended, in phoenixpico, 2-13 map, 4-7C4-9 shadow memory regions in phoenixpico, 2-12 supported, 2-18 system, in phoenixpico, 2-13 voltage, 2-19 see also dram and sram. memory management system viewer utility see mmsview.exe micropower off mode, 2-26 mms mmsa and mmsb windows, 3-3 resources accessible, 3-12 viewing system resources through, 3-12 mmsinfo.exe, 3-3 mmsinfo.zip, 3-3 mmsview.exe commands for, 3-14C3-17 syntax for, 3-13 using, 3-12C3-18 mmsview.zip, 3-4 mouse ps/2, see ps/2 mouse. n numlock setting in systemsoft, 2-7 o off mode power management, in, 2-24 setting in elanpmu, 3-7 os supported, xi oscillator, 32-khz layout suggestions, c-1 evalbd.book : evalbd.ix page 4 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-5 1.0 p p19, 2-21 p20, 2-21 p28, 2-21 p45, 2-21 parallel port setting, 2-21 setting base address, 3-11 setting for epp and bidirectional, 3-11 setting in systemsoft, 2-7 peripherals needed, 1-3 verified to work on board, b-1 pgp pins, 4-2C4-3 pgp0 pin, 4-2 pgp1 pin, 4-3 pgp2 pin, 4-3 pgp3 pin, 4-3 pgpa pin, 4-2 pgpb pin, 4-3 pgpc pin, 4-3 pgpd pin, 4-3 phoenixpico see bios. pirq1, 2-25 plls layout suggestions, c-2 pmc pins, 4-3C4-4 pmc0 pin, 4-4 pmc1 pin, 4-4 pmc2 pin, 4-4 pmc3 pin, 4-4 pmc4 pin, 4-4 pmu modes changing to current, 3-9 forcing, 3-8C3-9 restoring, 3-9 setting options, 3-5C3-7 power management enabling in phoenixpico, 2-14 enabling in systemsoft, 2-8 features, x layout suggestions, c-2 lowest mode, 2-26 power consumption, affecting, 3-4 simulation, 2-25 using, 2-24C2-25 power management control pins see pmc pins. power measurement jumpers, a-4 using, 2-23C2-24 processor speed setting in phoenixpico, 2-13 setting in systemsoft, 2-7 progammable general purpose pins see pgp pins. ps/2 mouse adding, 2-20 r ram, system displaying region, 3-12 read/compares, continuous performing, 3-12 regdump.exe, 3-4, 3-19 register dump utility see regdump.exe. registers manipulating, 3-19 reset pin, 4-4 rom sockets, 2-22 see also bios rom, dos rom, and application rom. rp1Crp2, rp3Crp4, 2-17 rstdrv pin, 4-4 rtc ram restrictions, 2-5 evalbd.book : evalbd.ix page 5 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-6 1.0 s sdb.exe, 3-4 sdb.zip, 3-4 serial ports internal, enabling, 4-15 serial port 1, 3-10 serial port 2, 3-10 setting addresses, 3-10C3-11 setting up, 2-21 setup screen setting in phoenixpico, 2-15 setting password in systemsoft, 2-8 setting to defaults in systemsoft, 2-9 simm restrictions, 2-4 sleep mode forcing, 3-8 power management, in, 2-24 setting in elanpmu, 3-7 super i/o setting port in systemsoft, 2-7 using, 4-14 suspend mode forcing, 3-9 power management, in, 2-24 setting in elanpmu, 3-7 toggling between it and high speed, 2- 25 suspend/resume button, 2-25 sw3-1, 2-18 sw3-1Csw3-4, a-3 sw3-2, 2-18 sw3-3, 2-18 sw3-4, 2-18 sw4, 3-9 sw4-1, 2-19 sw4-1Csw4-8, a-3 sw4-2, 2-25 sw4-3, 2-25 sw4-4Csw4-7, 2-24 sw4-8, 2-25 sw5, 2-26 switches list of, a-3 settings, a-1 system date and time setting in phoenixpico, 2-11 setting in systemsoft, 2-6 system memory, see memory, system. system ram filling with selected byte, 3-12 systemsoft, see bios. t timeouts setting in phoenixpico, 2-14C2-15 typematic rate in systemsoft, 2-8 u uarts connections to serial ports, 2-21 internal, 3-10 super i/o, 3-10 utilities, 3-2C3-4 evalbd.book : evalbd.ix page 6 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-7 1.0 v vgardy , 2-18 video display, setting in phoenixpico, 2-11 display, setting in systemsoft, 2-7 shadowing bios rom in phoenixpico, 2-12 shadowing in systemsoft, 2-8 view of data appending to log file, 3-12 vlrdyi , 2-18 vlrdyo , 2-18 voltage controlling, 4-5 vpp, 4-5 vrt bit, 2-6 evalbd.book : evalbd.ix page 7 thursday, august 8, 1996 2:34 pm
lansc310 microcontroller evaluation board users manual index-8 1.0 evalbd.book : evalbd.ix page 8 thursday, august 8, 1996 2:34 pm

▲Up To Search▲

Price & Availability of ELANSC310

	To Download ELANSC310 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .